Fitter report for float
Thu Nov 15 16:42:03 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Control Signals
 15. Global & Other Fast Signals
 16. Non-Global High Fan-Out Signals
 17. Fitter RAM Summary
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB-wide Signals
 21. LAB Signals Sourced
 22. LAB Signals Sourced Out
 23. LAB Distinct Inputs
 24. Fitter Device Options
 25. Advanced Data - General
 26. Advanced Data - Placement Preparation
 27. Advanced Data - Placement
 28. Advanced Data - Routing
 29. Fitter Messages
 30. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Thu Nov 15 16:42:03 2007         ;
; Quartus II Version    ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name         ; float                                         ;
; Top-level Entity Name ; float                                         ;
; Family                ; Cyclone                                       ;
; Device                ; EP1C3T144C8                                   ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 17 / 2,910 ( < 1 % )                          ;
; Total pins            ; 25 / 104 ( 24 % )                             ;
; Total virtual pins    ; 0                                             ;
; Total memory bits     ; 1,024 / 59,904 ( 2 % )                        ;
; Total PLLs            ; 0 / 1 ( 0 % )                                 ;
+-----------------------+-----------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C3T144C8                    ;                                ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Router Timing Optimization Level                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;