end if;end process;	Transmit_State_Machine:process(cp2,ireset)beginif (ireset='0') then                 -- ResetnUART_Tr_St0 <='0';UART_Tr_St1  <='0';UART_Tr_St2  <='0';UART_Tr_St3  <='0';UART_Tr_St4  <='0';UART_Tr_St5  <='0';UART_Tr_St6  <='0';UART_Tr_St7  <='0';UART_Tr_St8  <='0';UART_Tr_St9  <='0';UART_Tr_St10 <='0';UART_Tr_St11 <='0';  elsif (cp2='1' and cp2'event) then -- Clock   if (UART_Clk_En = '1') then       -- Clock enablenUART_Tr_St0 <= (not nUART_Tr_St0 and Flag_A) or (nUART_Tr_St0 and not(UART_Tr_St11 and not Flag_B));UART_Tr_St1  <= not UART_Tr_St1 and ((not nUART_Tr_St0 and Flag_A)or(UART_Tr_St11 and Flag_B));  -- Start bitUART_Tr_St2  <= UART_Tr_St1;										  -- Bit 0UART_Tr_St3  <=	UART_Tr_St2;										  -- Bit 1UART_Tr_St4  <=	UART_Tr_St3;										  -- Bit 2UART_Tr_St5  <=	UART_Tr_St4;										  -- Bit 3UART_Tr_St6  <=	UART_Tr_St5;										  -- Bit 4UART_Tr_St7  <=	UART_Tr_St6;										  -- Bit 5UART_Tr_St8  <=	UART_Tr_St7;										  -- Bit 6UART_Tr_St9  <=	UART_Tr_St8;										  -- Bit 7UART_Tr_St10 <= UART_Tr_St8 and CHR9_Latched;						  -- Bit 8 (if enabled)UART_Tr_St11 <=	(UART_Tr_St9 and not CHR9_Latched) or UART_Tr_St10;	  -- Stop bit   end if;  end if;end process;	-- USR bitsUSR_UDRE:process(cp2,ireset)beginif ireset='0' then                 -- Reset UDRE <= '1';	-- !!  elsif (cp2='1' and cp2'event) then -- Clock       UDRE <= (UDRE and not(UDR_Wr_En and (Flag_A or nUART_Tr_St0))) or (not UDRE and (UART_Tr_St11 and Flag_B and UART_Clk_En));	       end if;end process;		USR_Wr_En <= '1' when (adr=USR_Address and iowe='1') else '0';USR_TXC:process(cp2,ireset)beginif ireset='0' then                 -- Reset TXC <= '0';  elsif (cp2='1' and cp2'event) then -- Clock	  TXC <= (not TXC and(UART_Tr_St11 and not Flag_B and UART_Clk_En))or	        -- TXC set	??? (Is it possible to set TXC by writing zero(or one) to it?)	         (TXC and not(UDR_Wr_En or txc_irqack or (USR_Wr_En and dbus_in(6))));	-- TXC reset       end if;end process;			-- Transmitter IRQtxcirq  <= TXC and TXCIE;   udreirq <= UDRE and UDRIE;  -- Output enable signal(for external multiplexer control)out_en <= '1' when ((adr=UDR_Address or adr=UBRR_Address or adr=USR_Address or adr=UCR_Address) and                     iore='1') else '0';UCR_Wr_En <= '1' when (adr=UCR_Address and iowe='1') else '0';UCR_Bits:process(cp2,ireset)beginif ireset='0' then                          -- Reset	UCR(7 downto 2) <= (others => '0');  	UCR(0) <= '0'; elsif (cp2='1' and cp2'event) then         -- Clock  if UCR_Wr_En='1' then 			        -- Clock enable  	UCR(7 downto 2) <= dbus_in(7 downto 2);  	UCR(0) <= dbus_in(0);  end if;  end if;end process;			--*********************************** Receiver **************************************Receiver:process(cp2,ireset)beginif ireset='0' then                 -- ResetnUART_RcDel_St0 <='0';UART_RcDel_St1  <='0';UART_RcDel_St2  <='0';UART_RcDel_St3  <='0';UART_RcDel_St4  <='0';UART_RcDel_St5  <='0';UART_RcDel_St6  <='0';UART_RcDel_St7  <='0';UART_RcDel_St8  <='0';UART_RcDel_St9  <='0';UART_RcDel_St10 <='0';UART_RcDel_St11 <='0';UART_RcDel_St12 <='0';UART_RcDel_St13 <='0';UART_RcDel_St14 <='0';UART_RcDel_St15 <='0';UART_RcDel_St16 <='0';elsif (cp2='1' and cp2'event) then -- Clock  if Baud_Gen_Out='1' then 		   -- Clock enablenUART_RcDel_St0 <= (not nUART_RcDel_St0 and not RXD_ResyncB)or (nUART_RcDel_St0 and not((UART_RcDel_St10 and(Detector_Out and not nUART_Rc_St0))or -- Noise instead of start bit(UART_RcDel_St9 and UART_Rc_St10))); -- Stop bit was detectedUART_RcDel_St1  <= not UART_RcDel_St1 and((not nUART_RcDel_St0 and not RXD_ResyncB)or(UART_RcDel_St16 and nUART_Rc_St0));UART_RcDel_St2  <= UART_RcDel_St1;UART_RcDel_St3  <= UART_RcDel_St2;UART_RcDel_St4  <= UART_RcDel_St3;UART_RcDel_St5  <= UART_RcDel_St4;UART_RcDel_St6  <= UART_RcDel_St5;UART_RcDel_St7  <= UART_RcDel_St6;UART_RcDel_St8  <= UART_RcDel_St7;UART_RcDel_St9  <= UART_RcDel_St8;UART_RcDel_St10  <= not UART_RcDel_St10 and UART_RcDel_St9 and ((not Detector_Out and not nUART_Rc_St0)or(nUART_Rc_St0 and not UART_Rc_St10));UART_RcDel_St11 <= UART_RcDel_St10;UART_RcDel_St12 <= UART_RcDel_St11;UART_RcDel_St13 <= UART_RcDel_St12;UART_RcDel_St14 <= UART_RcDel_St13;UART_RcDel_St15 <= UART_RcDel_St14;UART_RcDel_St16 <= UART_RcDel_St15;	    end if;end if;end process;			UART_Rc_SR7_In <= UART_Rc_SR(8) when CHR9='1' else UART_Rc_SR(9);Receiver_Shift:process(cp2,ireset)beginif ireset='0' then                 -- ResetnUART_Rc_St0 <='0';UART_Rc_St1  <='0';UART_Rc_St2  <='0';UART_Rc_St3  <='0';UART_Rc_St4  <='0';UART_Rc_St5  <='0';UART_Rc_St6  <='0';UART_Rc_St7  <='0';UART_Rc_St8  <='0';UART_Rc_St9  <='0';UART_Rc_St10 <='0';UART_Rc_SR <= (others => '0'); elsif (cp2='1' and cp2'event) then -- Clock  if (Baud_Gen_Out and UART_RcDel_St9)='1' then 			 -- Clock enablenUART_Rc_St0 <= (not nUART_Rc_St0 and not RXD_ResyncB)or                 (nUART_Rc_St0 and not UART_Rc_St10);UART_Rc_St1  <= not UART_Rc_St1 and (not nUART_Rc_St0 and not RXD_ResyncB); -- D0UART_Rc_St2  <= UART_Rc_St1;                                                -- D1UART_Rc_St3  <= UART_Rc_St2;                                                -- D2UART_Rc_St4  <= UART_Rc_St3;                                                -- D3UART_Rc_St5  <= UART_Rc_St4;                                                -- D4UART_Rc_St6  <= UART_Rc_St5;                                                -- D5UART_Rc_St7  <= UART_Rc_St6;                                                -- D6UART_Rc_St8  <= UART_Rc_St7;                                                -- D7UART_Rc_St9  <= UART_Rc_St8 and CHR9;                                       -- D8UART_Rc_St10 <= (UART_Rc_St8 and not CHR9) or UART_Rc_St9;                  -- Stop bit   UART_Rc_SR(6 downto 0) <= UART_Rc_SR(7 downto 1);   UART_Rc_SR(7) <= UART_Rc_SR7_In;   UART_Rc_SR(8) <= UART_Rc_SR(9);   UART_Rc_SR(9) <= Detector_Out;  end if;end if;end process;			RXD_Resinc:process(cp2,ireset)beginif ireset='0' then                 -- Reset RXD_ResyncA <= '1'; RXD_ResyncB <= '1';  elsif (cp2='1' and cp2'event) then -- Clock  RXD_ResyncA <= rxd;  RXD_ResyncB <= RXD_ResyncA;  end if;end process;			Receiver_Detect_A:process(cp2,ireset)beginif ireset='0' then                 -- ResetDetector_A <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (Baud_Gen_Out and UART_RcDel_St7)='1' then -- Clock enable Detector_A <= RXD_ResyncB;end if;end if;end process;			Receiver_Detect_B:process(cp2,ireset)beginif ireset='0' then                 -- ResetDetector_B <= '0'; elsif (cp2='1' and cp2'event) then -- Clock if (Baud_Gen_Out and UART_RcDel_St8)='1' then -- Clock enable Detector_B <= RXD_ResyncB;end if;end if;end process;			Detector_Out <= (Detector_A and Detector_B)or(Detector_B and RXD_ResyncB)or(Detector_A and RXD_ResyncB);UDR_Rx_Reg:process(cp2,ireset)beginif ireset='0' then                 -- Reset UDR_Rx <= (others => '0'); FE     <= '0';					   -- Framing error elsif (cp2='1' and cp2'event) then -- Clockif (UART_Rc_Delay and RXEN and not RXC)='1' then -- Clock enable ??? TBD UDR_Rx <= UART_Rc_SR(7 downto 0); FE <= not UART_Rc_SR(9);          -- Framing error end if;end if;end process;			UCR_RXB8:process(cp2,ireset)beginif ireset='0' then                 -- Reset  RXB8 <= '1';                     -- ??? Check the papers againelsif (cp2='1' and cp2'event) then -- Clockif (UART_Rc_Delay and RXEN and not RXC and CHR9)='1' then -- Clock enable ??? TBD  RXB8 <= UART_Rc_SR(8);		   -- RXB8end if;end if;end process;			USR_Bits:process(cp2,ireset)beginif ireset='0' then                  -- ResetUSR(2 downto 0) <= (others => '0'); -- Reserved USR bitsRXC <= '0';DOR <= '0';UART_Rc_Delay <='0';elsif (cp2='1' and cp2'event) then -- ClockRXC <= (not RXC and (UART_Rc_Delay and RXEN))or(RXC and not UDR_Rd);DOR <= (not DOR and (UART_Rc_Delay and RXEN and RXC))or       (DOR and not (UART_Rc_Delay and RXEN and not RXC));UART_Rc_Delay <= not UART_Rc_Delay and (Baud_Gen_Out and UART_Rc_St10 and UART_RcDel_St9);end if;end process;			USR_Rd  <= '1' when (adr=USR_Address and iore='1') else '0';UCR_Rd  <= '1' when (adr=UCR_Address and iore='1') else '0';UBRR_Rd	<= '1' when (adr=UBRR_Address and iore='1') else '0';-- Output multiplexerOut_Mux: for i in dbus_out'range generatedbus_out(i) <= (UDR_Rx(i) and UDR_Rd)or			   (USR(i) and USR_Rd)or			   (UCR(i) and UCR_Rd)or               (UBRR(i) and UBRR_Rd);end generate; 	-- Reciever IRQrxcirq <= RXC and RXCIE;-- External linesrx_en <= RXEN;tx_en <= TXEN;end rtl;