`include "definitions.v"module latch_21bit ( data_in, data_out, phi);// Port Declarationsinput [20:0] data_in;output [20:0] data_out;input phi;reg [20:0] data_out;// latchalways @ (phi or data_in)begin  if (phi)    `LATCH_DELAY data_out <= data_in;endendmodule // latch_20bit