`include "definitions.v"// Need a Reset signal for reseting all occupied bits of CAMmodule control(phi1, phi2, cmd_s1, addr_s1, data_s1, lsb_addr_q1, msb_addr_s1,               cam_wen_q1, valid_s1, reset_cmd_s1, found_match_v2, addr_sel_s2,               ram_wen_q2, data_sel_s1, no_match_s1, data_mask_io_sel_s1,               port_io_sel_s1);input phi1;input phi2;input [1:0] cmd_s1;input [4:0] addr_s1;input [2:0] data_s1;         // port IDoutput [3:0] lsb_addr_q1;output [4:0] msb_addr_s1; //output [19:0] dec_addr_s1; //to changeoutput cam_wen_q1;output valid_s1;output reset_cmd_s1;input found_match_v2;output addr_sel_s2;output ram_wen_q2;output data_sel_s1;output [2:0] no_match_s1;    // default port IDoutput data_mask_io_sel_s1;  // sel for inout padsoutput port_io_sel_s1;       // sel for inout pads// output variableswire [3:0] lsb_addr_q1;reg [4:0] msb_addr_s1;//reg [19:0] dec_addr_s1;reg cam_wen_q1;reg valid_s1;reg reset_cmd_s1;reg addr_sel_s2;reg ram_wen_q2;reg data_sel_s1;reg [2:0] no_match_s1;reg data_mask_io_sel_s1; reg port_io_sel_s1;// local variableswire funky_addr_s1;reg driving_s1;//reg [3:0] lsb_addr_tmp_q1;wire [4:0] msb_addr_tmp_s1;   //reg [19:0] dec_addr_tmp_s1;reg [2:0] next_no_match_s1;reg [2:0] next_no_match_s2;reg [1:0] cmd_s2;reg funky_addr_s2;reg driving_s2;reg [1:0] prev_cmd_s1;reg prev_found_match_s1;reg prev_funky_addr_s1;reg prev_driving_s1;// auxiliary signals to generate control signalsassign funky_addr_s1 = (addr_s1 == `FUNKY_ADDR) ? 1'b1 : 1'b0;assign msb_addr_tmp_s1 = 0;assign lsb_addr_q1 = 0;   always @ (phi1 or cmd_s1 or funky_addr_s1 or data_s1 or no_match_s1 or msb_addr_tmp_s1)begin  case (cmd_s1)    `WRITE:      begin        cam_wen_q1   = 1'b1 & phi1;        valid_s1     = 1'b1;        reset_cmd_s1 = 1'b0;        if (funky_addr_s1) begin           // writing the no-match port ID	   msb_addr_s1 = 5'b00000;           next_no_match_s1 = data_s1[2:0];        end        else begin	   msb_addr_s1 = msb_addr_tmp_s1;           next_no_match_s1 = no_match_s1;        end      end    `SEARCH:      begin         cam_wen_q1   = 1'b1 & phi1;         valid_s1     = 1'b1;         reset_cmd_s1 = 1'b0;	 msb_addr_s1 = 5'b00000;         next_no_match_s1 = no_match_s1;      end    `READ:      begin         cam_wen_q1   = 1'b0 & phi1;         valid_s1     = 1'b1;  // really don't-care         reset_cmd_s1 = 1'b0;         if (funky_addr_s1) begin           // reading the no-match port ID	   msb_addr_s1 = 5'b00000;         end         else begin	   msb_addr_s1 = msb_addr_tmp_s1;         end         next_no_match_s1 = no_match_s1;      end    `DELETE:      begin         cam_wen_q1   = 1'b1 & phi1;         valid_s1     = 1'b0;         if (funky_addr_s1) begin           // this means reset-- this signal tells the           // CAM to clear the valid bits and tells our           // pads to not drive next           reset_cmd_s1 = 1'b1;	   // turn off word lines-- CAM valid bits are           // cleared with sneaky reset signal	   msb_addr_s1 = 5'b00000;         end         else begin           reset_cmd_s1 = 1'b0;	   msb_addr_s1 = msb_addr_tmp_s1;         end         next_no_match_s1 = no_match_s1;      end  endcaseend// storage between phase 1 and phase 2always @ (phi1 or cmd_s1 or funky_addr_s1 or driving_s1 or next_no_match_s1)begin  if (phi1) begin    cmd_s2           <= cmd_s1;    funky_addr_s2    <= funky_addr_s1;    driving_s2       <= driving_s1;    next_no_match_s2 <= next_no_match_s1;  endend// phase 2 control signalsalways @ (phi2 or cmd_s2) begin  case (cmd_s2)    `WRITE:      begin        addr_sel_s2 = `ADDR_SEL_CAM;        ram_wen_q2  = 1'b1 & phi2;      end    `SEARCH:      begin        addr_sel_s2 = `ADDR_SEL_PRI;        ram_wen_q2  = 1'b0 & phi2;      end    `READ:      begin        addr_sel_s2 = `ADDR_SEL_CAM;        ram_wen_q2  = 1'b0 & phi2;      end    `DELETE:      begin        addr_sel_s2 = `ADDR_SEL_CAM;        ram_wen_q2  = 1'b1 & phi2;   // don't-care for HW; testing requires 1      end  endcaseend// storage between phase 2 and phase 1always @ (phi2 or cmd_s2 or found_match_v2 or funky_addr_s2 or driving_s2 or          next_no_match_s2)begin  if (phi2) begin    prev_cmd_s1         <= cmd_s2;    prev_found_match_s1 <= found_match_v2;    prev_funky_addr_s1  <= funky_addr_s2;    prev_driving_s1     <= driving_s2;    no_match_s1         <= next_no_match_s2;  endend// set io select lines based on command one state agoalways @ (prev_driving_s1 or reset_cmd_s1 or prev_cmd_s1 or          prev_found_match_s1 or prev_funky_addr_s1)begin  if (prev_driving_s1 || reset_cmd_s1) begin    data_sel_s1 = `DATA_SEL_RAM;  // really don't-care    data_mask_io_sel_s1 = `PAD_SEL_IN;    port_io_sel_s1      = `PAD_SEL_IN;    driving_s1 = 1'b0;  end  else begin    case (prev_cmd_s1)      `WRITE,      `DELETE:        begin          data_sel_s1         = `DATA_SEL_RAM;  // really don't-care          data_mask_io_sel_s1 = `PAD_SEL_IN;          port_io_sel_s1      = `PAD_SEL_IN;          driving_s1          = 1'b0;        end      `SEARCH:        begin          if (prev_found_match_s1)            data_sel_s1       = `DATA_SEL_RAM;          else            data_sel_s1       = `DATA_SEL_NOMATCH;          data_mask_io_sel_s1 = `PAD_SEL_IN;          port_io_sel_s1      = `PAD_SEL_OUT;          driving_s1          = 1'b1;        end      `READ:        begin          if (prev_funky_addr_s1)            data_sel_s1       = `DATA_SEL_NOMATCH;          else            data_sel_s1       = `DATA_SEL_RAM;           data_mask_io_sel_s1 = `PAD_SEL_OUT;          port_io_sel_s1      = `PAD_SEL_OUT;          driving_s1          = 1'b1;        end    endcase  endendendmodule // control