Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Fri Aug 02 14:57:24 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd.   "csc_top" is an NCD, version 2.37, device xc2v80, package cs144, speed -4Loading device for application par from file '2v80.nph' in environment C:/ISE42.The STEPPING level for this design is 1.Device speed data version:  PRODUCTION 1.105 2002-05-09.Device utilization summary:   Number of External IOBs            51 out of 92     55%      Number of LOCed External IOBs    0 out of 51      0%   Number of SLICEs                  155 out of 512    30%   Number of BUFGMUXs                  1 out of 16      6%Overall effort level (-ol):   5 (set by user)Placer effort level (-pl):    5 (default)Placer cost table entry (-t): 1Router effort level (-rl):    5 (default)Extra effort level (-xe):     1 (default)Starting initial Timing Analysis.  REAL time: 0 secs Finished initial Timing Analysis.  REAL time: 0 secs Starting Clock Logic Placement.  REAL time: 2 secs Finished Clock Logic Placement.  REAL time: 2 secs Automatic resolution of clock placement was successful.It was not necessary to constrain the placement of any of the logic driven by
the global clocks with the current clock placement.######################################################## Automatic clock placement completed.######################################################Starting clustering phase.  REAL time: 5 secs Finished clustering phase.  REAL time: 6 secs Dumping design to file csc_top.ncd.Starting Directed Placer.  REAL time: 6 secs Placement pass 1 ....Placer score = 45190Placer score = 45190Finished Directed Placer.  REAL time: 6 secs Starting Constructive Placer.  REAL time: 6 secs Placer score = 45270Placer score = 40220Placer score = 37670Placer score = 35700Placer score = 35255Placer score = 33810Placer score = 32950Placer score = 31175Placer score = 30030Placer score = 29840Placer score = 29495Placer score = 28515Placer score = 28430Placer score = 28335Placer score = 28085Placer score = 28040Placer score = 27830Finished Constructive Placer.  REAL time: 8 secs Dumping design to file csc_top.ncd.Starting Optimizing Placer.  REAL time: 8 secs Optimizing  Swapped 58 comps.Xilinx Placer [1]   26630   REAL time: 9 secs Optimizing  Swapped 11 comps.Xilinx Placer [2]   26510   REAL time: 9 secs Finished Optimizing Placer.  REAL time: 9 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 9 secs Total CPU time to Placer completion: 9 secs 0 connection(s) routed; 1261 unrouted active, 23 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 9 secs Starting iterative routing. Routing active signals................End of iteration 1 1284 successful; 0 unrouted; (0) REAL time: 12 secs Constraints are met. Total REAL time: 12 secs Total CPU  time: 11 secs End of route.  1284 routed (100.00%); 0 unrouted.No errors found. WARNING:Route:49 - The signal "GLOBAL_LOGIC0" has no loads so was not routed. Total REAL time to Router completion: 12 secs Total CPU time to Router completion: 11 secs Generating PAR statistics.   The Delay Summary Report   The Score for this design is: 5198The Number of signals not completely routed for this design is: 0   The Average Connection Delay for this design is:        1.275 ns   The Maximum Pin Delay is:                               5.069 ns   The Average Connection Delay on the 10 Worst Nets is:   3.539 ns   Listing Pin Delays by value: (ns)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00   ---------   ---------   ---------   ---------   ---------   ---------         693         251         203         127          10           0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic                                             |            |            | Levels--------------------------------------------------------------------------------  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 10.734ns   | 8      S   HIGH 50.000000 %                      |            |            |      --------------------------------------------------------------------------------  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 4.718ns    | 3    --------------------------------------------------------------------------------  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 8.705ns    | 1    --------------------------------------------------------------------------------All constraints were met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 13 secs Total CPU time to PAR completion: 12 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.