Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Fri Aug 02 15:14:39 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd.   "csc_top" is an NCD, version 2.37, device xc2v80, package cs144, speed -4Loading device for application par from file '2v80.nph' in environment C:/ISE42.The STEPPING level for this design is 1.Device speed data version:  PRODUCTION 1.105 2002-05-09.Device utilization summary:   Number of External IOBs            63 out of 92     68%      Number of LOCed External IOBs    0 out of 63      0%   Number of SLICEs                  178 out of 512    34%   Number of BUFGMUXs                  1 out of 16      6%Overall effort level (-ol):   5 (set by user)Placer effort level (-pl):    5 (default)Placer cost table entry (-t): 1Router effort level (-rl):    5 (default)Extra effort level (-xe):     1 (default)Starting initial Timing Analysis.  REAL time: 4 secs Finished initial Timing Analysis.  REAL time: 5 secs Starting Clock Logic Placement.  REAL time: 6 secs Finished Clock Logic Placement.  REAL time: 6 secs Automatic resolution of clock placement was successful.It was not necessary to constrain the placement of any of the logic driven by
the global clocks with the current clock placement.######################################################## Automatic clock placement completed.######################################################Starting clustering phase.  REAL time: 15 secs Finished clustering phase.  REAL time: 17 secs Starting Mincut Placer.  REAL time: 17 secs Finished Mincut Placer.  REAL time: 17 secs Dumping design to file csc_top.ncd.Starting Directed Placer.  REAL time: 18 secs Placement pass 1 ......Placer score = 53595Placer score = 53595Finished Directed Placer.  REAL time: 18 secs Starting Constructive Placer.  REAL time: 19 secs Placer score = 53465Placer score = 50835Placer score = 46100Placer score = 44480Placer score = 42210Placer score = 39130Placer score = 37775Placer score = 36600Placer score = 36000Placer score = 35325Placer score = 35205Placer score = 34035Placer score = 33720Placer score = 33330Placer score = 32925Placer score = 32595Placer score = 32580Finished Constructive Placer.  REAL time: 23 secs Dumping design to file csc_top.ncd.Starting Optimizing Placer.  REAL time: 23 secs Optimizing  Swapped 53 comps.Xilinx Placer [1]   31320   REAL time: 23 secs Optimizing  Swapped 9 comps.Xilinx Placer [2]   31240   REAL time: 23 secs Finished Optimizing Placer.  REAL time: 23 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 24 secs Total CPU time to Placer completion: 9 secs 0 connection(s) routed; 1492 unrouted active, 23 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 24 secs Starting iterative routing. Routing active signals...........End of iteration 1 1515 successful; 0 unrouted; (0) REAL time: 28 secs Constraints are met. Total REAL time: 28 secs Total CPU  time: 12 secs End of route.  1515 routed (100.00%); 0 unrouted.No errors found. WARNING:Route:49 - The signal "GLOBAL_LOGIC0" has no loads so was not routed. Total REAL time to Router completion: 28 secs Total CPU time to Router completion: 12 secs Generating PAR statistics.   The Delay Summary Report   The Score for this design is: 5188The Number of signals not completely routed for this design is: 0   The Average Connection Delay for this design is:        1.197 ns   The Maximum Pin Delay is:                               5.377 ns   The Average Connection Delay on the 10 Worst Nets is:   3.444 ns   Listing Pin Delays by value: (ns)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00   ---------   ---------   ---------   ---------   ---------   ---------         825         355         214         108          13           0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic                                             |            |            | Levels--------------------------------------------------------------------------------  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 9.647ns    | 6      S   HIGH 50.000000 %                      |            |            |      --------------------------------------------------------------------------------  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 5.223ns    | 3    --------------------------------------------------------------------------------  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 8.705ns    | 1    --------------------------------------------------------------------------------All constraints were met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 30 secs Total CPU time to PAR completion: 12 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.