?? csc_top.par
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Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Fri Aug 02 15:15:14 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd. "csc_top" is an NCD, version 2.37, device xcv50e, package cs144, speed -6Loading device for application par from file 'v50e.nph' in environment C:/ISE42.Device speed data version: PRELIMINARY 1.65 2001-12-19.Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 62 out of 94 65% Number of LOCed External IOBs 0 out of 62 0% Number of SLICEs 173 out of 768 22% Number of GCLKs 1 out of 4 25%Overall effort level (-ol): 5 (set by user)Placer effort level (-pl): 5 (default)Placer cost table entry (-t): 1Router effort level (-rl): 5 (default)Extra effort level (-xe): 1 (default)Starting initial Timing Analysis. REAL time: 4 secs Finished initial Timing Analysis. REAL time: 7 secs Starting initial Placement phase. REAL time: 8 secs Finished initial Placement phase. REAL time: 9 secs Starting the placer. REAL time: 9 secs Placement pass 1 .Placer score = 38860Placement pass 2 .Placer score = 39035Optimizing ... Placer score = 38285Placer score = 38210Placer score = 38165Placer score = 38150Placer score = 38121Placer score = 38106Placer score = 38076Placer score = 38060Placer score = 38075Placer score = 38090Placer stage completed in real time: 10 secs Optimizing ... Placer score = 35340Placer completed in real time: 11 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 12 secs Total CPU time to Placer completion: 2 secs 0 connection(s) routed; 1267 unrouted active, 24 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 13 secs Starting iterative routing. Routing active signals......End of iteration 1 1291 successful; 0 unrouted; (0) REAL time: 17 secs Constraints are met. Total REAL time: 17 secs Total CPU time: 4 secs End of route. 1291 routed (100.00%); 0 unrouted.No errors found. Completely routed. Total REAL time to Router completion: 17 secs Total CPU time to Router completion: 4 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 286The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 1.941 ns The Maximum Pin Delay is: 7.915 ns The Average Connection Delay on the 10 Worst Nets is: 4.642 ns Listing Pin Delays by value: (ns) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 8.00 d >= 8.00 --------- --------- --------- --------- --------- --------- 445 341 168 179 158 0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- NET "Clock_ibuf/IBUFG" PERIOD = 12.500 n | 12.500ns | 10.421ns | 9 S HIGH 50.000000 % | | | -------------------------------------------------------------------------------- OFFSET = IN 9.500 nS BEFORE COMP "Clock" | 9.500ns | 9.249ns | 3 -------------------------------------------------------------------------------- OFFSET = OUT 9.500 nS AFTER COMP "Clock" | 9.500ns | 6.453ns | 1 --------------------------------------------------------------------------------All constraints were met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 19 secs Total CPU time to PAR completion: 5 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.
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