Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Fri Aug 02 15:13:52 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd.   "csc_top" is an NCD, version 2.37, device xcv50, package tq144, speed -4Loading device for application par from file 'v50.nph' in environment C:/ISE42.Device speed data version:  FINAL 1.116 2001-12-19.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            62 out of 98     63%      Number of LOCed External IOBs    0 out of 62      0%   Number of SLICEs                  173 out of 768    22%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   5 (set by user)Placer effort level (-pl):    5 (default)Placer cost table entry (-t): 1Router effort level (-rl):    5 (default)Extra effort level (-xe):     1 (default)Starting initial Timing Analysis.  REAL time: 0 secs Finished initial Timing Analysis.  REAL time: 2 secs Starting initial Placement phase. REAL time: 2 secs Finished initial Placement phase. REAL time: 2 secs Starting the placer. REAL time: 2 secs Placement pass 1 .Placer score = 37495Placement pass 2 .Placer score = 39089Placement pass 3 ......Placer score = 38812Placement pass 4 ..Placer score = 37776Placement pass 5 .Placer score = 36816Placement pass 6 .Placer score = 38349Optimizing ... Placer score = 38049Placer score = 37829Placer score = 37609Placer score = 37519Placer score = 37272Placer score = 37242Placer score = 36929Placer score = 37005Placer score = 36989Placer score = 36884Placer score = 36914Placer score = 36809Placer score = 36749Placer score = 36824Placer score = 36914Placer score = 36749Placer score = 36704Placer score = 36704Placer score = 36659Placer score = 36674Placer score = 36629Placer score = 36509Placer score = 36494Placer score = 36449Placer score = 36434Placer score = 36434Placer stage completed in real time: 4 secs Optimizing ... Placer score = 33435Placer completed in real time: 4 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 4 secs Total CPU time to Placer completion: 3 secs 0 connection(s) routed; 1267 unrouted active, 24 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 4 secs Starting iterative routing. Routing active signals.................End of iteration 1 1291 successful; 0 unrouted; (0) REAL time: 15 secs Constraints are met. Total REAL time: 15 secs Total CPU  time: 14 secs End of route.  1291 routed (100.00%); 0 unrouted.No errors found. Completely routed. Total REAL time to Router completion: 15 secs Total CPU time to Router completion: 14 secs Generating PAR statistics.   The Delay Summary Report   The Score for this design is: 315The Number of signals not completely routed for this design is: 0   The Average Connection Delay for this design is:        2.169 ns   The Maximum Pin Delay is:                               8.387 ns   The Average Connection Delay on the 10 Worst Nets is:   4.940 ns   Listing Pin Delays by value: (ns)    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 9.00  d >= 9.00   ---------   ---------   ---------   ---------   ---------   ---------         625         474         168          22           2           0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic                                             |            |            | Levels--------------------------------------------------------------------------------  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 12.361ns   | 9      S   HIGH 50.000000 %                      |            |            |      --------------------------------------------------------------------------------  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 9.187ns    | 3    --------------------------------------------------------------------------------  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 7.870ns    | 1    --------------------------------------------------------------------------------All constraints were met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 16 secs Total CPU time to PAR completion: 15 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.