Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Fri Aug 02 15:20:38 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd.   "csc_top" is an NCD, version 2.37, device xc2vp2, package fg256, speed -6Loading device for application par from file '2vp2.nph' in environment C:/ISE42.Device speed data version:  ADVANCED 1.56 2002-05-15.Device utilization summary:   Number of External IOBs            63 out of 140    45%      Number of LOCed External IOBs    0 out of 63      0%   Number of SLICEs                  287 out of 1408   20%   Number of BUFGMUXs                  1 out of 16      6%Overall effort level (-ol):   5 (set by user)Placer effort level (-pl):    5 (default)Placer cost table entry (-t): 1Router effort level (-rl):    5 (default)Extra effort level (-xe):     1 (default)Starting initial Timing Analysis.  REAL time: 19 secs Finished initial Timing Analysis.  REAL time: 24 secs Starting Clock Logic Placement.  REAL time: 28 secs Finished Clock Logic Placement.  REAL time: 28 secs Automatic resolution of clock placement was successful.It was not necessary to constrain the placement of any of the logic driven by
the global clocks with the current clock placement.######################################################## Automatic clock placement completed.######################################################Starting clustering phase.  REAL time: 47 secs Finished clustering phase.  REAL time: 51 secs Dumping design to file csc_top.ncd.Starting Directed Placer.  REAL time: 52 secs Placement pass 1 ....Placer score = 94180Placer score = 94180Finished Directed Placer.  REAL time: 54 secs Starting Constructive Placer.  REAL time: 54 secs Placer score = 76060Placer score = 68725Placer score = 63560Placer score = 61230Finished Constructive Placer.  REAL time: 59 secs Dumping design to file csc_top.ncd.Starting Optimizing Placer.  REAL time: 1 mins Optimizing  Swapped 76 comps.Xilinx Placer [1]   59265   REAL time: 1 mins Optimizing  Swapped 7 comps.Xilinx Placer [2]   59205   REAL time: 1 mins 1 secs Finished Optimizing Placer.  REAL time: 1 mins 1 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 1 mins 2 secs Total CPU time to Placer completion: 11 secs 0 connection(s) routed; 2058 unrouted active, 33 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 1 mins 5 secs Starting iterative routing. Routing active signals.............End of iteration 1 2091 successful; 0 unrouted; (0) REAL time: 1 mins 15 secs Constraints are met. Total REAL time: 1 mins 16 secs Total CPU  time: 14 secs End of route.  2091 routed (100.00%); 0 unrouted.No errors found. WARNING:Route:49 - The signal "GLOBAL_LOGIC0" has no loads so was not routed. Total REAL time to Router completion: 1 mins 17 secs Total CPU time to Router completion: 15 secs Generating PAR statistics.   The Delay Summary Report   The Score for this design is: 5149The Number of signals not completely routed for this design is: 0   The Average Connection Delay for this design is:        0.907 ns   The Maximum Pin Delay is:                               5.337 ns   The Average Connection Delay on the 10 Worst Nets is:   2.964 ns   Listing Pin Delays by value: (ns)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00   ---------   ---------   ---------   ---------   ---------   ---------        1267         562         214          34          14           0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic                                             |            |            | Levels--------------------------------------------------------------------------------  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 8.177ns    | 14     S   HIGH 50.000000 %                      |            |            |      --------------------------------------------------------------------------------  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 5.339ns    | 3    --------------------------------------------------------------------------------  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 6.280ns    | 1    --------------------------------------------------------------------------------All constraints were met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 1 mins 21 secs Total CPU time to PAR completion: 15 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.