Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Fri Aug 02 15:20:30 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd.   "csc_top" is an NCD, version 2.37, device xcv50e, package cs144, speed -6Loading device for application par from file 'v50e.nph' in environment C:/ISE42.Device speed data version:  PRELIMINARY 1.65 2001-12-19.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            62 out of 94     65%      Number of LOCed External IOBs    0 out of 62      0%   Number of SLICEs                  283 out of 768    36%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   5 (set by user)Placer effort level (-pl):    5 (default)Placer cost table entry (-t): 1Router effort level (-rl):    5 (default)Extra effort level (-xe):     1 (default)Starting initial Timing Analysis.  REAL time: 8 secs Finished initial Timing Analysis.  REAL time: 13 secs Starting initial Placement phase. REAL time: 15 secs Finished initial Placement phase. REAL time: 16 secs Starting the placer. REAL time: 16 secs Placement pass 1 ...Placer score = 53415Placement pass 2 ....Placer score = 58946Placement pass 3 .............................................Placer score = 56843Placement pass 4 .................................Placer score = 52093Placement pass 5 ...................................Placer score = 53025Placement pass 6 ................................Placer score = 58503Optimizing ... Placer score = 50934Placer score = 50868Placer score = 51120Placer score = 51114Placer score = 50882Placer score = 50829Placer score = 50983Placer score = 51064Placer score = 51031Placer score = 50899Placer score = 50854Placer score = 50749Placer score = 50806Placer score = 50731Placer score = 50584Placer score = 50584Placer score = 50569Placer score = 50491Placer score = 50476Placer score = 50461Placer score = 50461Placer stage completed in real time: 29 secs Optimizing ... Placer score = 45487Placer completed in real time: 31 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 33 secs Total CPU time to Placer completion: 5 secs 0 connection(s) routed; 1783 unrouted active, 37 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 34 secs Starting iterative routing. Routing active signals...............Optimizing (468)..............................................................................................................End of iteration 1 1820 successful; 0 unrouted; (419) REAL time: 1 mins 27 secs End of iteration 2 1820 successful; 0 unrouted; (419) REAL time: 1 mins 36 secs ..End of iteration 3 1820 successful; 0 unrouted; (411) REAL time: 1 mins 56 secs ..End of iteration 4 1820 successful; 0 unrouted; (411) REAL time: 2 mins 12 secs Ending automatic router iterations. Total REAL time: 2 mins 12 secs Total CPU  time: 34 secs End of route.  1820 routed (100.00%); 0 unrouted.No errors found. Completely routed. The design submitted for place and route did not meet the specified timing
requirements.  Please use the static timing analysis tools (TRCE or Timing
Analyzer) to report which constraints were not met.  To obtain a better result,
you may try the following:  * Use the Re-entrant routing feature to run more router iterations on the
design.  * Check the timing constraints to make sure the design is not
over-constrained.  * Specify a higher placer effort level, if possible.  * Use the Multi-Pass PAR (MPPR) feature.  This generates multiple placement
trials from which the best (i.e., lowest design score) placement can be used
with re-entrant routing to obtain a better result.Please consult the Development System Reference Guide for more detailed
information about the usage options pertaining to these features.Total REAL time to Router completion: 2 mins 13 secs Total CPU time to Router completion: 35 secs Generating PAR statistics.   The Delay Summary Report   The Score for this design is: 1340The Number of signals not completely routed for this design is: 0   The Average Connection Delay for this design is:        2.183 ns   The Maximum Pin Delay is:                              10.369 ns   The Average Connection Delay on the 10 Worst Nets is:   5.675 ns   Listing Pin Delays by value: (ns)    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 11.00  d >= 11.00   ---------   ---------   ---------   ---------   ---------   ---------        1099         432         150          88          51           0Timing Score: 411WARNING:Par:62 - Timing constraints have not been met.Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic                                             |            |            | Levels--------------------------------------------------------------------------------* NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 12.911ns   | 14     S   HIGH 50.000000 %                      |            |            |      --------------------------------------------------------------------------------  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 8.635ns    | 3    --------------------------------------------------------------------------------  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 6.465ns    | 1    --------------------------------------------------------------------------------1 constraint not met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 2 mins 15 secs Total CPU time to PAR completion: 35 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - 1 errors found.PAR done.