Place SLICE CSC_module/cb_g_kcm(10) in site CLB_R7C13.S0.Resolved that SLICE <CSC_module/Cb_KCM_red/un1_un1_color_1(12)> must be placed
at site CLB_R9C9.S0.   Place SLICE CSC_module/Cb_KCM_red/un1_un1_color_1(12) in site CLB_R9C9.S0.Resolved that SLICE <CSC_module/Cb_KCM_green/un1_un1_color_0(12)> must be placed
at site CLB_R7C13.S1.   Place SLICE CSC_module/Cb_KCM_green/un1_un1_color_0(12) in site CLB_R7C13.S1.Resolved that SLICE <CSC_module/cb_cst_b(9)> must be placed at site CLB_R9C9.S1.   Place SLICE CSC_module/cb_cst_b(9) in site CLB_R9C9.S1.Resolved that SLICE <CSC_module/cr_g_kcm(19)> must be placed at site
CLB_R3C14.S0.   Place SLICE CSC_module/cr_g_kcm(19) in site CLB_R3C14.S0.Resolved that SLICE <cb_sig(7)> must be placed at site CLB_R2C6.S0.   Place SLICE cb_sig(7) in site CLB_R2C6.S0.Resolved that SLICE <CSC_module/y_g_kcm(21)> must be placed at site
CLB_R3C14.S1.   Place SLICE CSC_module/y_g_kcm(21) in site CLB_R3C14.S1.Resolved that GCLK <Clock_ibuf/BUFG> must be placed at site GCLKBUF1.   Place GCLK Clock_ibuf/BUFG in site GCLKBUF1.Resolved that SLICE <CSC_module/Y601_KCM_red/un2_0(22)> must be placed at site
CLB_R1C1.S0.   Place SLICE CSC_module/Y601_KCM_red/un2_0(22) in site CLB_R1C1.S0.Resolved that SLICE <CSC_module/Cb_KCM_red/un1_un1_color_0(14)> must be placed
at site CLB_R4C2.S0.   Place SLICE CSC_module/Cb_KCM_red/un1_un1_color_0(14) in site CLB_R4C2.S0.Resolved that SLICE <CSC_module/Cr_KCM_green/un1_un1_color_0(17)> must be placed
at site CLB_R4C15.S0.   Place SLICE CSC_module/Cr_KCM_green/un1_un1_color_0(17) in site CLB_R4C15.S0.Resolved that SLICE <CSC_module/Cb_KCM_red/un1_un1_color_1(20)> must be placed
at site CLB_R6C9.S0.   Place SLICE CSC_module/Cb_KCM_red/un1_un1_color_1(20) in site CLB_R6C9.S0.Resolved that SLICE <CSC_module/Cr_KCM_green/un1_un1_color_1(19)> must be placed
at site CLB_R4C16.S0.   Place SLICE CSC_module/Cr_KCM_green/un1_un1_color_1(19) in site CLB_R4C16.S0.Resolved that SLICE <CSC_module/y_g_kcm(22)> must be placed at site
CLB_R2C10.S0.   Place SLICE CSC_module/y_g_kcm(22) in site CLB_R2C10.S0.Resolved that SLICE <CSC_module/Y601_KCM_red/un2_0(21)> must be placed at site
CLB_R1C2.S1.   Place SLICE CSC_module/Y601_KCM_red/un2_0(21) in site CLB_R1C2.S1.Resolved that SLICE <CSC_module/Cb_KCM_red/un1_un1_color_1(18)> must be placed
at site CLB_R3C2.S0.   Place SLICE CSC_module/Cb_KCM_red/un1_un1_color_1(18) in site CLB_R3C2.S0.Resolved that SLICE <CSC_module/Cb_KCM_red/un1_un1_color_1(19)> must be placed
at site CLB_R2C2.S1.   Place SLICE CSC_module/Cb_KCM_red/un1_un1_color_1(19) in site CLB_R2C2.S1.Resolved that SLICE <CSC_module/Cr_KCM_green/un1_un1_color_1(18)> must be placed
at site CLB_R4C16.S1.   Place SLICE CSC_module/Cr_KCM_green/un1_un1_color_1(18) in site CLB_R4C16.S1.Resolved that SLICE <CSC_module/y_cst_g(15)> must be placed at site
CLB_R7C11.S1.   Place SLICE CSC_module/y_cst_g(15) in site CLB_R7C11.S1.Resolved that SLICE <CSC_module/cb_g_kcm(20)> must be placed at site
CLB_R2C13.S0.   Place SLICE CSC_module/cb_g_kcm(20) in site CLB_R2C13.S0.Resolved that SLICE <CSC_module/cb_r_kcm(6)> must be placed at site CLB_R8C8.S0.   Place SLICE CSC_module/cb_r_kcm(6) in site CLB_R8C8.S0.Resolved that SLICE <CSC_module/y_cst_g(4)> must be placed at site
CLB_R11C10.S0.   Place SLICE CSC_module/y_cst_g(4) in site CLB_R11C10.S0.Resolved that SLICE <CSC_module/y_cst_g(5)> must be placed at site
CLB_R10C12.S1.   Place SLICE CSC_module/y_cst_g(5) in site CLB_R10C12.S1.Resolved that SLICE <CSC_module/y_g_kcm(3)> must be placed at site
CLB_R11C13.S0.   Place SLICE CSC_module/y_g_kcm(3) in site CLB_R11C13.S0.Resolved that SLICE <CSC_module/y_g_kcm(4)> must be placed at site
CLB_R11C12.S1.   Place SLICE CSC_module/y_g_kcm(4) in site CLB_R11C12.S1.Resolved that SLICE <CSC_module/y_b_kcm(20)> must be placed at site CLB_R1C7.S0.   Place SLICE CSC_module/y_b_kcm(20) in site CLB_R1C7.S0.Resolved that SLICE <CSC_module/y_g_kcm(2)> must be placed at site CLB_R11C8.S0.   Place SLICE CSC_module/y_g_kcm(2) in site CLB_R11C8.S0.Resolved that SLICE <CSC_module/y_b_kcm(0)> must be placed at site CLB_R12C8.S0.   Place SLICE CSC_module/y_b_kcm(0) in site CLB_R12C8.S0.Resolved that SLICE <CSC_module/cr_b_kcm(16)> must be placed at site
CLB_R2C10.S1.   Place SLICE CSC_module/cr_b_kcm(16) in site CLB_R2C10.S1.Resolved that SLICE <CSC_module/y_r_kcm(2)> must be placed at site CLB_R11C1.S1.   Place SLICE CSC_module/y_r_kcm(2) in site CLB_R11C1.S1.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            62 out of 98     63%      Number of LOCed External IOBs    0 out of 62      0%   Number of SLICEs                  285 out of 768    37%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   5 (set by user)Placer effort level (-pl):    5 (default)Placer cost table entry (-t): 1Router effort level (-rl):    5 (default)Extra effort level (-xe):     1 (default)Starting initial Timing Analysis.  REAL time: 0 secs Finished initial Timing Analysis.  REAL time: 0 secs Starting initial Placement phase. REAL time: 0 secs Finished initial Placement phase. REAL time: 0 secs Starting the placer. REAL time: 0 secs Placement pass 1 .Placer score = 53775Placement pass 2 .Placer score = 68138Placement pass 3 .Placer score = 66451Placement pass 4 .Placer score = 68371Placement pass 5 .Placer score = 66434Placement pass 6 .Placer score = 68375Optimizing ... Placer score = 64104Placer score = 63650Placer score = 63357Placer score = 63354Placer score = 63330Placer score = 63275Placer score = 63138Placer score = 63122Placer score = 63122Placer score = 63105Placer stage completed in real time: 3 secs Optimizing ... Placer score = 56704Placer completed in real time: 3 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 3 secs Total CPU time to Placer completion: 3 secs 0 connection(s) routed; 1785 unrouted active, 37 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 4 secs Starting iterative routing. Routing active signals.....................Optimizing (9777)..............................................................................End of iteration 1 1822 successful; 0 unrouted; (11342) REAL time: 19 secs ...End of iteration 2 1822 successful; 0 unrouted; (11114) REAL time: 36 secs WARNING:Route:260 - Routing for this placement is not expected to meet the
   current timing constraints.  Change the placement, modify the timing
   constraints or reduce the number of logic levels in the paths that are not
   meeting timing.Total REAL time: 36 secs Total CPU  time: 36 secs End of route.  1822 routed (100.00%); 0 unrouted.No errors found. Completely routed. The design submitted for place and route did not meet the specified timing
requirements.  Please use the static timing analysis tools (TRCE or Timing
Analyzer) to report which constraints were not met.  To obtain a better result,
you may try the following:  * Use the Re-entrant routing feature to run more router iterations on the
design.  * Check the timing constraints to make sure the design is not
over-constrained.  * Specify a higher placer effort level, if possible.  * Use the Multi-Pass PAR (MPPR) feature.  This generates multiple placement
trials from which the best (i.e., lowest design score) placement can be used
with re-entrant routing to obtain a better result.Please consult the Development System Reference Guide for more detailed
information about the usage options pertaining to these features.Total REAL time to Router completion: 36 secs Total CPU time to Router completion: 36 secs Generating PAR statistics.   The Delay Summary Report   The Score for this design is: 20558The Number of signals not completely routed for this design is: 0   The Average Connection Delay for this design is:        2.348 ns   The Maximum Pin Delay is:                               9.317 ns   The Average Connection Delay on the 10 Worst Nets is:   5.063 ns   Listing Pin Delays by value: (ns)    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 10.00  d >= 10.00   ---------   ---------   ---------   ---------   ---------   ---------         934         631         130          54          73           0Timing Score: 11114WARNING:Par:62 - Timing constraints have not been met.Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic                                             |            |            | Levels--------------------------------------------------------------------------------* NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 15.303ns   | 14     S   HIGH 50.000000 %                      |            |            |      --------------------------------------------------------------------------------  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 8.999ns    | 3    --------------------------------------------------------------------------------  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 7.870ns    | 1    --------------------------------------------------------------------------------1 constraint not met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 37 secs Total CPU time to PAR completion: 37 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - 20 errors found.PAR done.