Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Fri Aug 02 15:10:25 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd.   "csc_top" is an NCD, version 2.37, device xc2s50e, package tq144, speed -6Loading device for application par from file '2s50e.nph' in environment
C:/ISE42.Device speed data version:  PRELIMINARY 1.11 2002-05-10.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            50 out of 98     51%      Number of LOCed External IOBs    0 out of 50      0%   Number of SLICEs                  236 out of 768    30%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   5 (set by user)Placer effort level (-pl):    5 (default)Placer cost table entry (-t): 1Router effort level (-rl):    5 (default)Extra effort level (-xe):     1 (default)Starting initial Timing Analysis.  REAL time: 0 secs Finished initial Timing Analysis.  REAL time: 2 secs Starting initial Placement phase. REAL time: 2 secs Finished initial Placement phase. REAL time: 2 secs Starting the placer. REAL time: 2 secs Placement pass 1 .Placer score = 41835Placement pass 2 ....Placer score = 42224Placement pass 3 .......................Placer score = 42252Placement pass 4 ..............Placer score = 40838Placement pass 5 ..........Placer score = 42277Placement pass 6 .........................................................Placer score = 45662Optimizing ... Placer score = 43647Placer score = 43382Placer score = 43172Placer score = 43172Placer score = 43024Placer score = 43039Placer score = 43054Placer score = 43114Placer score = 43054Placer score = 43084Placer score = 42964Placer score = 42889Placer score = 42814Placer score = 42814Placer score = 42799Placer score = 42769Placer score = 42769Placer stage completed in real time: 4 secs Optimizing ... Placer score = 38865Placer completed in real time: 4 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 4 secs Total CPU time to Placer completion: 4 secs 0 connection(s) routed; 1483 unrouted active, 30 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 5 secs Starting iterative routing. Routing active signals.........End of iteration 1 1513 successful; 0 unrouted; (0) REAL time: 7 secs Constraints are met. Total REAL time: 7 secs Total CPU  time: 6 secs End of route.  1513 routed (100.00%); 0 unrouted.No errors found. Completely routed. Total REAL time to Router completion: 7 secs Total CPU time to Router completion: 6 secs Generating PAR statistics.   The Delay Summary Report   The Score for this design is: 285The Number of signals not completely routed for this design is: 0   The Average Connection Delay for this design is:        1.859 ns   The Maximum Pin Delay is:                               6.569 ns   The Average Connection Delay on the 10 Worst Nets is:   5.002 ns   Listing Pin Delays by value: (ns)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 7.00  d >= 7.00   ---------   ---------   ---------   ---------   ---------   ---------         598         327         227         160         201           0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.--------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic                                             |            |            | Levels--------------------------------------------------------------------------------  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 11.863ns   | 10     S   HIGH 50.000000 %                      |            |            |      --------------------------------------------------------------------------------  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 8.737ns    | 3    --------------------------------------------------------------------------------  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 6.465ns    | 1    --------------------------------------------------------------------------------All constraints were met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 8 secs Total CPU time to PAR completion: 7 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - No errors found.PAR done.