#ifndef __DMA_H__
#define __DMA_H__

#define XSDMA_CHANNEL_MAX		15
#define XSDMA_CHANNEL_NUM		(XSDMA_CHANNEL_MAX + 1)
#define DMA_REGISTER_BASE		0x40000000

typedef enum XsDmaDrcmrIdE
{
    XSDMA_DRCMR_ID_DREQ_0         = 0, // companion chip request 0
    XSDMA_DRCMR_ID_DREQ_1         = 1, // companion chip request 1
    XSDMA_DRCMR_ID_I2S_RX         = 2, // I2S receive request
    XSDMA_DRCMR_ID_I2S_TX         = 3, // I2S transmit request
    XSDMA_DRCMR_ID_BTUART_RX      = 4, // BTUART receive request
    XSDMA_DRCMR_ID_BTUART_TX      = 5, // BTUART transmit request
    XSDMA_DRCMR_ID_FFUART_RX      = 6, // FFUART receive request
    XSDMA_DRCMR_ID_FFUART_TX      = 7, // FFUART transmit request
    XSDMA_DRCMR_ID_AC97_MIC_RX    = 8, // AC97 microphone request
    XSDMA_DRCMR_ID_AC97_MODEM_RX  = 9, // AC97 MODEM receive request
    XSDMA_DRCMR_ID_AC97_MODEM_TX  = 10, // AC97 MODEM transmit request
    XSDMA_DRCMR_ID_AC97_AUDIO_RX  = 11, // AC97 Audio receive request
    XSDMA_DRCMR_ID_AC97_AUDIO_TX  = 12, // AC97 Audio transmit request
    XSDMA_DRCMR_ID_SSP_RX         = 13, // SSP receive request
    XSDMA_DRCMR_ID_SSP_TX         = 14, // SSP transmit request
    XSDMA_DRCMR_ID_RSVD_15        = 15, // reserved
    XSDMA_DRCMR_ID_RSVD_16        = 16, // reserved
    XSDMA_DRCMR_ID_FICP_RX        = 17, // ICP receive request
    XSDMA_DRCMR_ID_FICP_TX        = 18, // ICP transmit request
    XSDMA_DRCMR_ID_STUART_RX      = 19, // STUART receive request
    XSDMA_DRCMR_ID_STUART_TX      = 20, // STUART transmit request
    XSDMA_DRCMR_ID_MMC_RX         = 21, // MMC receive request
    XSDMA_DRCMR_ID_MMC_TX         = 22, // MMC transmit request
    XSDMA_DRCMR_ID_RSVD_23        = 23, // reserved
    XSDMA_DRCMR_ID_RSVD_24        = 24, // reserved
    XSDMA_DRCMR_ID_USB_CLNT_EP_1  = 25, // USB endpoint 1 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_2  = 26, // USB endpoint 2 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_3  = 27, // USB endpoint 3 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_4  = 28, // USB endpoint 4 request
    XSDMA_DRCMR_ID_RSVD_29        = 29, // reserved
    XSDMA_DRCMR_ID_USB_CLNT_EP_6  = 30, // USB endpoint 6 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_7  = 31, // USB endpoint 7 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_8  = 32, // USB endpoint 8 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_9  = 33, // USB endpoint 9 request
    XSDMA_DRCMR_ID_RSVD_34        = 34, // reserved
    XSDMA_DRCMR_ID_USB_CLNT_EP_11 = 35, // USB endpoint 11 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_12 = 36, // USB endpoint 12 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_13 = 37, // USB endpoint 13 request
    XSDMA_DRCMR_ID_USB_CLNT_EP_14 = 38, // USB endpoint 14 request
    XSDMA_DRCMR_ID_RSVD_39        = 39, // reserved
    XSDMA_DRCMR_ID_MAX            = XSDMA_DRCMR_ID_RSVD_39,
    XSDMA_DRCMR_ID_NUM            = (XSDMA_DRCMR_ID_MAX+1),
    XSDMA_DRCMR_ID_ILLEGAL        = XSDMA_DRCMR_ID_NUM,
    // Memory doesn't have a DRCMR.  Define this for users of records
    //  where XsDmaDrcmrIdT values are stored.
    XSDMA_DRCMR_ID_MEMORY         = (XSDMA_DRCMR_ID_NUM+1)

} XsDmaDrcmrIdT;

typedef struct XsDmaDescriptorGroupS {
    VUINT32   DDADR;  // descriptor address reg
    VUINT32   DSADR;  // source address register
    VUINT32   DTADR;  // target address register
    VUINT32   DCMD;   // command address register
} XsDmaDescriptorGroupT;

typedef struct XsDmaCtrlS {
    VUINT32   DCSR[XSDMA_CHANNEL_NUM]; //DMA CSRs by channel

    UINT32    PAD0[44];  // unused addresses
    VUINT32   DINT;        // DMA interrupt register
    UINT32    PAD1[3];   // unused addresses

                           // Indexed by the XsDmaDrcmrIdT enums.
    VUINT32   DRCMR[XSDMA_DRCMR_ID_NUM];
    UINT32      PAD2[24];  
    XsDmaDescriptorGroupT DDG[XSDMA_CHANNEL_NUM]; // DMA descriptor group array

} XsDmaCtrlT;

//volatile XsDmaCtrlT * XsDmaControlRegsP = (XsDmaCtrlT *)DMA_REGISTER_BASE;
extern volatile XsDmaCtrlT * XsDmaControlRegsP;

#endif