/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document.    
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       XsAc97Ctrl.c
**
**  PURPOSE:        Driver for the main processor's on-board AC'97 Controller
**                  device.  Includes initialization, API and support
**                  functions.  Corresponds to DM_AC97ControllerUnit_LLD.doc.
**
**  Valid for    :  Subset of AC '97 Rev 2.1
**
**  Valid for    :  Cotulla processor
**
**  EAS VERSION  :  2.1
**
**  $Modtime: 6/28/01 9:18a $ 
******************************************************************************/

#define _DEFINING_XSAC97CTRL

#include "string.h"
#include "systypes.h"
#include "errors.h"
#include "XsIntCtrlApi.h"
#include "Ac97MixerRegsApi.h"
#include "XsAc97CtrlApi.h"
#include "XsAc97Ctrl.h"
#include "xsClkMgr.h"

#define DM_WaitMs Util_DelayMs
#define DM_WaitUs Util_DelayUs
#include "UtilFunc.h"
#include "XsUartDrv.h"

/*
*******************************************************************************
   Functions in standard driver API of main processor on-board AC'97 Controller
*******************************************************************************
*/

UINT32 Ac97CheckRegId (AC97MixerRegisterIdT registerIdToCheck)
{
    UINT32 status = ERR_NONE;

    // Register must be in range and also even.  No odd registers supported
    //  by the spec.

    if ( (registerIdToCheck < 0 ) || 
         (registerIdToCheck > AC97_MR_MAX)|| 
         (registerIdToCheck & 1) )
    {
        status = ERR_T_ILLPARAM;
    }
    return (status);
    
} // Ac97CheckRegId ()


/*
*******************************************************************************
*
* FUNCTION:         XsAc97CtrlSWInit
*
* DESCRIPTION:      Init context structure and private table.
*
* INPUT PARAMETERS: None
*
* RETURNS:          None
*
* GLOBAL EFFECTS:   None
*
* ASSUMPTIONS:      
*
* CALLS:            XsAc97CtrlSetStatusEntry
*
* CALLED BY:        
*
* PROTOTYPE:        void XsAc97CtrlSWInit (void);
*
*******************************************************************************
*/

void XsAc97CtrlSWInit (void)
{

    // Zero AC'97 Controller context structure
    memset (&XsAc97CtrlContext, 0, sizeof(XsAc97CtrlContext));

    //
    // Initialize the status indicators table, which also serves as the
    //   registered interrupt (callback) processing table
    // All interrupt types set to disabled, with no registered handler or param
    //

    // CODEC GPI Status Change
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_GSCI], 
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->GCR,              // enableRegisterP
        XS_AC97CTRL_GCR_GIE_SH,             // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_GSCI_SH,            // reportBitShiftGsr
        &XsAc97CtrlRegsP->GSR,              // clearRegisterP
        XS_AC97CTRL_GSR_GSCI_SH);           // clearBitShift

    // MODEM In
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_MDM_IN],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->MICR,             // enableRegisterP
        XS_AC97CTRL_FIFO_ERR_CTRL_SHFT,     // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_MIINT_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->MISR,             // clearRegisterP
        XS_AC97CTRL_FIFO_ERR_STAT_SHFT);    // clearBitShift

    // MODEM Out
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_MDM_OUT],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->MOCR,             // enableRegisterP
        XS_AC97CTRL_FIFO_ERR_CTRL_SHFT,     // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_MOINT_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->MOSR,             // clearRegisterP
        XS_AC97CTRL_FIFO_ERR_STAT_SHFT);    // clearBitShift

    // PCM In
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCM_IN],
        TRUE,                               // intIsSupported
        &XsAc97CtrlRegsP->PICR,             // enableRegisterP
        XS_AC97CTRL_FIFO_ERR_CTRL_SHFT,     // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_PIINT_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->PISR,             // clearRegisterP
        XS_AC97CTRL_FIFO_ERR_STAT_SHFT);    // clearBitShift

    // PCM Out
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCM_OUT],
        TRUE,                               // intIsSupported
        &XsAc97CtrlRegsP->POCR,             // enableRegisterP
        XS_AC97CTRL_FIFO_ERR_CTRL_SHFT,     // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_POINT_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->POSR,             // clearRegisterP
        XS_AC97CTRL_FIFO_ERR_STAT_SHFT);    // clearBitShift

    // Mic In
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_MIC_IN],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->MCCR,             // enableRegisterP
        XS_AC97CTRL_FIFO_ERR_CTRL_SHFT,     // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_MINT_SH,            // reportBitShiftGsr
        &XsAc97CtrlRegsP->MCSR,             // clearRegisterP
        XS_AC97CTRL_FIFO_ERR_STAT_SHFT);    // clearBitShift

    // Primary CODEC Ready
    // Difficult to support via interrupt; special handling would be required
    //  in the ISR and in other parts of the code because the indication for  
    //  this normal status cannot be cleared and the interrupt is level
    //  triggered, not edge (event) triggered.
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCRDY],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->GCR,              // enableRegisterP
        XS_AC97CTRL_GCR_PCRDY_IEN_SH,       // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_PCRDY_SH,           // reportBitShiftGsr
        NULL,                               // clearRegisterP: Can't clear
        0 );                                // clearBitShift:  Can't clear

    // Secondary CODEC Ready
    // Difficult to support via interrupt; special handling would be required
    //  in the ISR and in other parts of the code because the indication for  
    //  this normal status cannot be cleared and the interrupt is level
    //  triggered, not edge (event) triggered.
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SCRDY],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->GCR,              // enableRegisterP
        XS_AC97CTRL_GCR_SCRDY_IEN_SH,       // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_SCRDY_SH,           // reportBitShiftGsr
        NULL,                               // clearRegisterP: Can't clear
        0 );                                // clearBitShift:  Can't clear

    // Primary Resume
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_PCRSM],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->GCR,              // enableRegisterP
        XS_AC97CTRL_GCR_PCRSM_IEN_SH,       // enableBitShift
        1u,                                 // reportBitMaskGsr,
        XS_AC97CTRL_GSR_PCRSM_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->GSR,              // clearRegisterP
        XS_AC97CTRL_GSR_PCRSM_SH );         // clearBitShift

    // Secondary Resume
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SCRSM],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->GCR,              // enableRegisterP
        XS_AC97CTRL_GCR_SCRSM_IEN_SH,       // enableBitShift
        1u,                                 // reportBitMaskGsr,
        XS_AC97CTRL_GSR_SCRSM_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->GSR,              // clearRegisterP
        XS_AC97CTRL_GSR_SCRSM_SH );         // clearBitShift

    // Bits1..3 of Slot 12
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SLT12_B1_3],
        FALSE,                              // intIsSupported:  No interrupt
        NULL,                               // enableRegisterP: No interrupt
        0,                                  // enableBitShift:  No interrupt
        7u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_SCRSM_SH,           // reportBitShiftGsr
        NULL,                               // clearRegisterP: Can't clear
        0 );                                // clearBitShift:  Can't clear

    // Read Completion Status (error)
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_RCS_ERR],
        FALSE,                              // intIsSupported:  No interrupt
        NULL,                               // enableRegisterP: No interrupt
        0,                                  // enableBitShift:  No interrupt
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_SCRSM_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->GSR,              // clearRegisterP
        XS_AC97CTRL_GSR_SCRSM_SH );         // clearBitShift

    // Status Done
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_SDONE],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->GCR,              // enableRegisterP
        XS_AC97CTRL_GCR_SDONE_IE_SH,        // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_SDONE_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->GSR,              // clearRegisterP
        XS_AC97CTRL_GSR_SDONE_SH );         // clearBitShift

    // Command Done
    XsAc97CtrlSetStatusEntry (&XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_CDONE],
        FALSE,                              // intIsSupported
        &XsAc97CtrlRegsP->GCR,              // enableRegisterP
        XS_AC97CTRL_GCR_CDONE_IE_SH,        // enableBitShift
        1u,                                 // reportBitMaskGsr
        XS_AC97CTRL_GSR_CDONE_SH,           // reportBitShiftGsr
        &XsAc97CtrlRegsP->GSR,              // clearRegisterP
        XS_AC97CTRL_GSR_CDONE_SH );         // clearBitShift

    //
    // End Initialize registered interrupt processing table
    //

} // End XsAc97CtrlSWInit ()


/*
*******************************************************************************
*
* FUNCTION:         XsAc97CtrlHWSetup
*
* DESCRIPTION:      Register the AC'97 Controller interrupt handling  
*                     subroutine with the Interrupt Controller driver module.
*                   Enable AC'97 Controller device clock.
*                   Perform a cold reset of the AC'97 controller and codec(s).
*                   Enable AC'97 Controller interrupts at the Int Controller.
*                   Note: Does not enable any interrupt types within the 
*                     ACUNIT, so no interrupts should occur at this point.
*
* INPUT PARAMETERS: None
*
* RETURNS:   
*       Success:    0 (ERR_NONE)
*       Failure:    ERR_T_SW_INTERNAL: Internal SW error in this module or a
*                                      subroutine.  For details, examine the 
*                                      error history.
*                   ERR_T_NOBITSET: Clock manager failed to enable ACUNIT clock
*                   ERR_T_TIMEOUT:  Took too long for at least one codec to 
*                                   respond as ready, after cold reset.
*
* GLOBAL EFFECTS:   Error logged before return.
*
* ASSUMPTIONS:      - No other systems, such as debuggers, are using the 
*                     AC '97 Controller or codecs, or the AC Link.
*                   - The software system will be unharmed by a cold reset of 
*                     the entire AC '97 subsystem and any associated devices.
*
* CALLS:            
*
* CALLED BY:        
*
* PROTOTYPE:        UINT32 XsAc97CtrlHWSetup (void);
*
*******************************************************************************
*/

UINT32 XsAc97CtrlHWSetup(void)
{ 
    UINT32 status;













    status = xsCMEnableClock (AC97_CE);


    if (!status)
    {
        // Perform the cold reset.
        // Also enables the codec(s), control unit and the control unit's FIFOs
        status = XsAc97CtrlColdReset ();