#define UCB_RR      0x00    // Reset Register
#define UCB_MVR     0x02    // Master Volume Register
#define UCB_HVR     0x04    // Reserved
#define UCB_MNVR    0x06    // Reserved
#define UCB_PBVR    0x0A    // Reserved
#define UCB_PVR     0x0C    // Reserved
#define UCB_MICVR   0x0E    // MIC Volume Register
#define UCB_LINVR   0x10    // Reserved
#define UCB_CDVR    0x12    // Reserved
#define UCB_VVR     0x14    // Reserved
#define UCB_AUXVR   0x16    // Reserved
#define UCB_POUTVR  0x18    // Reserved
#define UCB_RSR     0x1A    // Record Select Register
#define UCB_RGR     0x1C    // Record Gain Register
#define UCB_GPR     0x20    // General Purpose Register
#define UCB_3DCR    0x22    // Reserved
#define UCB_PCSR    0x26    // Powerdown Ctrl/Status Register
#define UCB_EAIDR   0x28    // Extended Audio ID Register
#define UCB_EASCR   0x2A    // Extended Audio Status/Ctrl Register
#define UCB_ADR     0x2C    // Audio DAC Sample Rate Register
#define UCB_AAR     0x32    // Audio ADC Sample Rate Register
#define UCB_EMIDR   0x3C    // Reserved
#define UCB_EMSCR   0x3E    // Reserved
#define UCB_GPCR    0x4C    // Reserved
#define UCB_GPPTR   0x4E    // Reserved
#define UCB_GPSTCR  0x50    // Reserved
#define UCB_GPWMR   0x52    // Reserved
#define UCB_GPSR    0x54    // Reserved
#define UCB_ACMCR   0x5E    // Positive INT Enable Register
#define UCB_MCCR    0x60    // Negative INT Enable Register
#define UCB_SPDIFCR 0x68    // ADC Data Register
#define UCB_SPCR    0x6A    // Feature CSR1 Register
#define UCB_VID1    0x7C    // Vendor ID1 Register
#define UCB_VID2    0x7E    // Vendor ID2 Register


#define UCB_RSR_SR_SHIFT    0
#define UCB_RSR_SR_CL       ( 0x0 << UCB_RSR_SR_SHIFT ) // copy from left
#define UCB_RSR_SR_LINE     ( 0x100 << UCB_RSR_SR_SHIFT )

#define UCB_RSR_SL_SHIFT    8
#define UCB_RSR_SL_MIC      ( 0x0 << UCB_RSR_SL_SHIFT )
#define UCB_RSR_SL_LINE     ( 0x100 << UCB_RSR_SL_SHIFT )

#define UCB_EAIDR_VRA   ( 0x1 << 0 )    // Variable Rate PCM Audio supported
#define UCB_DR_22050    0x5622  // 22050 samples/sec
#define UCB_DR_48000    0xBB80  // 48000 samples/sec