/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       XsAc97Ctrl.h
**
**  PURPOSE:        Constants, structure and variable declarations for the 
**                  internal usage of the main processor's on-board
**                  AC'97 Controller device driver.
**                  - Includes initialization materials
**
**  Valid for    :  Subset of AC '97 Rev 2.1
**
**  Valid for    :  Cotulla processor
**
**  EAS VERSION  :  2.1
**
**  $Modtime: 6/28/01 9:19a $ 
******************************************************************************/
#include "systypes.h"
#include "Ac97MixerRegsApi.h"
#include "XsAc97CtrlApi.h"

#ifndef _XSAC97CTRL_H
#define _XSAC97CTRL_H



/*
*******************************************************************************
*******************************************************************************
***   Constant definitions
*******************************************************************************
*******************************************************************************/

// Error sub-location codes for ERR_L_XSAC97CTRL location code

#define ERR_S_XSAC97CTRL_HWSETUP        0x01 // XsAc97HWSetup
#define ERR_S_XSAC97CTRL_REG_HANDLER    0x02 // XsAc97CtrlRegisterHandler
#define ERR_S_XSAC97CTRL_UNR_HANDLER    0x03 // XsAc97CtrlUnRegisterHandler
#define ERR_S_XSAC97CTRL_DISAB_INT      0x04 // XsAc97CtrlDisableIntType
#define ERR_S_XSAC97CTRL_ENAB_INT       0x05 // XsAc97CtrlEnableIntType
#define ERR_S_XSAC97CTRL_COLD_RESET     0x06 // XsAc97CtrlColdReset
#define ERR_S_XSAC97CTRL_GET_STATUS     0x07 // XsAc97CtrlGetStatus
#define ERR_S_XSAC97CTRL_CODEC_READ     0x08 // XsAc97CtrlCodecRead
#define ERR_S_XSAC97CTRL_CODEC_WRITE    0x09 // XsAc97CtrlCodecWrite
#define ERR_S_XSAC97CTRL_CLEAR_STATUS   0x0A // XsAc97CtrlClearStatus
#define ERR_S_XSAC97CTRL_INT_HANDLER    0x0B // XsAc97CtrlInterruptHandler


/*******************************************************************************
    Physical memory address of GPIO AC'97 Controller Register base
     - System architecture sets virtual addresses the same as the 
       physical addresses for I/O space.
*******************************************************************************
*/

#define XS_AC97CTRL_REGISTER_BASE   0x40500000

#define XS_AC97CTRL_FIFO_ERR_STAT_SHFT  4
#define XS_AC97CTRL_FIFO_ERR_STAT_BIT  (1u << XS_AC97CTRL_FIFO_ERR_STAT_SHFT)


                // XS_AC97CTRL_FIFO_ERR_CTRL_SHFT is used in:
                                                // POCR
                                                // PICR
                                                // MCCR
                                                // MOCR
                                                // MICR
#define XS_AC97CTRL_FIFO_ERR_CTRL_SHFT  3
#define XS_AC97CTRL_FIFO_ERR_CTRL_BIT  (1u << XS_AC97CTRL_FIFO_ERR_CTRL_SHFT)

/*
*******************************************************************************
    Constants for the Global Control Register and Global Status Register
    - Where possible, the symbolic name matches that in the processor manual
      - One exception is the Primary Ready and Secondary Ready interrupts. 
    - All undefined bits are reserved.
*******************************************************************************
*/

// Global Control Register bit shift constants

#define XS_AC97CTRL_GCR_GIE_SH            0 // CODEC GPI Interrupt Enable (GIE)
#define XS_AC97CTRL_GCR_COLD_RESET_SH     1 // AC'97 Cold Reset#.
#define XS_AC97CTRL_GCR_WARM_RESET_SH     2 // AC97 Warm Reset.
#define XS_AC97CTRL_GCR_LINK_OFF_SH       3 // ACLINK Shut Off:
#define XS_AC97CTRL_GCR_PCRSM_IEN_SH      4 // Primary Resume Interrupt Enable
#define XS_AC97CTRL_GCR_SCRSM_IEN_SH      5 // Secondary Resume Int Enable
#define XS_AC97CTRL_GCR_PCRDY_IEN_SH      8 // Primary Ready Interrupt Enable
#define XS_AC97CTRL_GCR_SCRDY_IEN_SH      9 // Secondary Ready Interrupt Enable
#define XS_AC97CTRL_GCR_SDONE_IE_SH      18 // Status Done Interrupt Enable
#define XS_AC97CTRL_GCR_CDONE_IE_SH      19 // Command Done Interrupt Enable

// Global Control Register bit mask constants

#define XS_AC97CTRL_GCR_GIE_MSK          (1u << XS_AC97CTRL_GCR_GIE_SH)
#define XS_AC97CTRL_GCR_COLD_RESET_MSK   (1u << XS_AC97CTRL_GCR_COLD_RESET_SH)
#define XS_AC97CTRL_GCR_WARM_RESET_MSK   (1u << XS_AC97CTRL_GCR_WARM_RESET_SH)
#define XS_AC97CTRL_GCR_LINK_OFF_MSK     (1u << XS_AC97CTRL_GCR_LINK_OFF_SH)
#define XS_AC97CTRL_GCR_PCRSM_IEN_MSK    (1u << XS_AC97CTRL_GCR_PCRSM_IEN_SH)
#define XS_AC97CTRL_GCR_SCRSM_IEN_MSK    (1u << XS_AC97CTRL_GCR_SCRSM_IEN_SH)
#define XS_AC97CTRL_GCR_PCRDY_IEN_MSK    (1u << XS_AC97CTRL_GCR_PCRDY_IEN_SH)
#define XS_AC97CTRL_GCR_SCRDY_IEN_MSK    (1u << XS_AC97CTRL_GCR_SCRDY_IEN_SH)
#define XS_AC97CTRL_GCR_SDONE_IE_MSK     (1u << XS_AC97CTRL_GCR_SDONE_IE_SH)
#define XS_AC97CTRL_GCR_CDONE_IE_MSK     (1u << XS_AC97CTRL_GCR_CDONE_IE_SH)


// Global Status Register bit shift constants
//  Terminating substring is truncated to "SH" to remain within 32 char limit.

#define XS_AC97CTRL_GSR_GSCI_SH            0  // CODEC GPI Status Change Int
#define XS_AC97CTRL_GSR_MIINT_SH           1  // MODEM In Interrupt 	
#define XS_AC97CTRL_GSR_MOINT_SH           2  // MODEM Out Interrupt	
#define XS_AC97CTRL_GSR_PIINT_SH           5  // PCM In Interrupt     	
#define XS_AC97CTRL_GSR_POINT_SH           6  // PCM  Out Interrupt	
#define XS_AC97CTRL_GSR_MINT_SH            7  // Mic In Interrupt     	
#define XS_AC97CTRL_GSR_PCRDY_SH           8  // Primary CODEC Ready	
#define XS_AC97CTRL_GSR_SCRDY_SH           9  // Secondary CODEC Ready	
#define XS_AC97CTRL_GSR_PCRSM_SH          10  // Primary Resume Interrupt
#define XS_AC97CTRL_GSR_SCRSM_SH          11  // Secondary Resume Interrupt
#define XS_AC97CTRL_GSR_SLT12_B1_BASE_SH  12  // Base of Bits1..3 of Slot 12
#define XS_AC97CTRL_GSR_RCS_ERR_SH        15  // Read Completion Status (error)
#define XS_AC97CTRL_GSR_SDONE_SH          18  // Status Done
#define XS_AC97CTRL_GSR_CDONE_SH          19  // Command Done

// Global Status Register bit mask constants

#define XS_AC97CTRL_GSR_GSCI_MSK       (1u << XS_AC97CTRL_GSR_GSCI_SH)
#define XS_AC97CTRL_GSR_MIINT_MSK      (1u << XS_AC97CTRL_GSR_MIINT_SH)
#define XS_AC97CTRL_GSR_MOINT_MSK      (1u << XS_AC97CTRL_GSR_MOINT_SH)
#define XS_AC97CTRL_GSR_PIINT_MSK      (1u << XS_AC97CTRL_GSR_PIINT_SH)
#define XS_AC97CTRL_GSR_POINT_MSK      (1u << XS_AC97CTRL_GSR_POINT_SH)
#define XS_AC97CTRL_GSR_MINT_MSK       (1u << XS_AC97CTRL_GSR_MINT_SH)
#define XS_AC97CTRL_GSR_PCRDY_MSK      (1u << XS_AC97CTRL_GSR_PCRDY_SH)
#define XS_AC97CTRL_GSR_SCRDY_MSK      (1u << XS_AC97CTRL_GSR_SCRDY_SH)
#define XS_AC97CTRL_GSR_PCRSM_MSK      (1u << XS_AC97CTRL_GSR_PCRSM_SH)
#define XS_AC97CTRL_GSR_SCRSM_MSK      (1u << XS_AC97CTRL_GSR_SCRSM_SH
#define XS_AC97CTRL_GSR_SLT12_BITS_MSK (7u << XS_AC97CTRL_GSR_SLT12_B1_BASE_SH)
#define XS_AC97CTRL_GSR_RCS_ERR_MSK    (1u << XS_AC97CTRL_GSR_RCS_ERR_SH)
#define XS_AC97CTRL_GSR_SDONE_MSK      (1u << XS_AC97CTRL_GSR_SDONE_SH)
#define XS_AC97CTRL_GSR_CDONE_MSK      (1u << XS_AC97CTRL_GSR_CDONE_SH)

/*
*******************************************************************************
    Other constants
*******************************************************************************
*/

        // The period of an AC Link frame in microseconds (10^6 / 48,000)