#define XS_AC97CTRL_ACLINK_FRAME_USECS     21

        // The number of 50 microsecond intervals to hold the cold reset
        //   line active before deactivating it, in order to perform a
        //   cold reset.
        // The minimum value of this constant is codec-dependent and should
        //  be determined by the least responsive codec in the system.
#define XS_AC97CTRL_COLD_HOLD_50USECS       1

        // The number of 50 microsecond intervals to wait before declaring
        //   a time out on receipt of a Codec Ready indication after Bit 1
        //   of the GSR is toggled from 0 to 1.
        // The minimum value of this constant is codec-dependent and should
        //  be determined by the least responsive codec in the system.
#define XS_AC97CTRL_COLD_TIMEOUT_50USECS    10

        // Timeout for the I/O cycle reading mixer registers from Codec
        // Actually the max is expected to be 126 uSec; add some for padding
#define XS_AC97CTRL_READ_TIMEOUT_1USECS ((XS_AC97CTRL_ACLINK_FRAME_USECS*6)+24)

#define XS_AC97CTRL_CODEC_READ_RETRIES       3

        // Getting the AC link should not take much longer than a time-out
        //  on an in-progress read operation.  If one read operation is 
        //  successful, both should proceed fairly quickly.
#define XS_AC97CTRL_CAIP_TIMEOUT_1USECS  (XS_AC97CTRL_READ_TIMEOUT_1USECS + 50)


/*
*******************************************************************************
    AC'97 Controller Registers Structure Definition
*******************************************************************************
*/

// For accessing the Codec mixer registers, each increment of one 32-bit word
//  in processor space increments the addressed mixer register by two.
// This does not cause any ambiguities because only even mixer register 
//  addresses are currently supported (AC '97 spec, R 2.2)
#define XS_AC97CTRL_MIXER_REGS_PER_WORD   2


typedef struct XsAc97CtrlRegsS
{  //   Register symbol     // Usage

    VUINT32 POCR;           // PCM Out Control Register
    VUINT32 PICR;           // PCM In Control Register
    VUINT32 MCCR;           // Mic In Control Register
    VUINT32 GCR;            // Global Control Register
    VUINT32 POSR;           // PCM Out Status Register
    VUINT32 PISR;           // PCM In Status Register
    VUINT32 MCSR;           // Mic In Status Register
    VUINT32 GSR;            // Global Status Register
    VUINT32 CAR;            // CODEC Access Register
    VUINT32 rsvd1 [7];      // 0x4050-0024 through 0x4050-003C
    VUINT32 PCDR;           // PCM FIFO Data Register
    VUINT32 rsvd2 [7];      // 0x4050-0044 through 0x4050-005C   
    VUINT32 MCDR;           // Mic-in FIFO Data Register
    VUINT32 rsvd3 [0x27];   // 0x4050-0064 through 0x4050-00FC   
    VUINT32 MOCR;           // MODEM Out Control Register
    VUINT32 rsvd4; 
    VUINT32 MICR;           // MODEM In Control Register
    VUINT32 rsvd5; 
    VUINT32 MOSR;           // MODEM Out Status Register
    VUINT32 rsvd6; 
    VUINT32 MISR;           // MODEM In Status Register
    VUINT32 rsvd7 [9];      // 0x4050-011C through 0x4050-013C
    VUINT32 MODR;           // MODEM FIFO Data Register 
    VUINT32 rsvd8 [0x2F];   // 0x4050-0144 through 0x4050-01FC
                            // Primary Audio CODEC registers access 
    VUINT32 XsAC97CtrlMixerRegsPrimaryAud   [AC97_NUM_MIXER_REGS];
                            // Secondary Audio CODEC registers access
    VUINT32 XsAC97CtrlMixerRegsSecondaryAud [AC97_NUM_MIXER_REGS];
                            // Primary MODEM CODEC registers access
    VUINT32 XsAC97CtrlMixerRegsPrimaryMdm   [AC97_NUM_MIXER_REGS];
                            // Secondary MODEM CODEC registers access
    VUINT32 XsAC97CtrlMixerRegsSecondaryMdm [AC97_NUM_MIXER_REGS];

}  XsAc97CtrlRegsT ;

/*
*******************************************************************************
    Define one entry in the AC'97 Controller status indicator processing table.
    Includes interrupt control and callback (registered handler) info.
*******************************************************************************
*/

typedef struct XsAc97CtrlStatusEntryE
{
    BOOL     intIsSupported;           // Int supported in current system?
    BOOL     intIsEnabled;             // Ints currently enabled for this type?

    void*    registeredParamP;         // Pass back to registered handler

    VUINT32* enableRegisterP;          // Addr of mem-mapped reg for int enable
    INT      enableBitShift;           // Bit position in enable reg for enable

    UINT32   reportBitMaskGsr;         // Unshifted Mask for status in GSR
    INT      reportBitShiftGsr;        // Bit position where reported in GSR

    VUINT32* clearRegisterP;           // Addr of mem-mapped reg for status clr
    INT      clearBitShift;            // Bit position in status reg for clear

} XsAc97CtrlStatusEntryT;

extern XsAc97CtrlStatusEntryT XsAc97CtrlStatusTable [XS_AC97CTRL_STAT_MAX+1];

/*
*******************************************************************************
*******************************************************************************
    Ac97Ctrl.c scope variable definitions
*******************************************************************************
*******************************************************************************
*/
extern const XsAc97CtrlStatusIdT XsAc97CtrlIntToStatusTransTbl [] ;
/*
static
XsAc97CtrlStatusIdT XsAc97CtrlIntToStatusTransTbl [] =
{
    XS_AC97CTRL_STAT_GSCI,    // XS_AC97CTRL_INT_GSCI
    XS_AC97CTRL_STAT_MDM_IN,  // XS_AC97CTRL_INT_MIINT
    XS_AC97CTRL_STAT_MDM_OUT, // XS_AC97CTRL_INT_MOINT
    XS_AC97CTRL_STAT_PCM_IN,  // XS_AC97CTRL_INT_PIINT
    XS_AC97CTRL_STAT_PCM_OUT, // XS_AC97CTRL_INT_POINT
    XS_AC97CTRL_STAT_MIC_IN,  // XS_AC97CTRL_INT_MINT 
    XS_AC97CTRL_STAT_PCRDY,   // XS_AC97CTRL_INT_PCRDY
    XS_AC97CTRL_STAT_SCRDY,   // XS_AC97CTRL_INT_SCRDY
    XS_AC97CTRL_STAT_PCRSM,   // XS_AC97CTRL_INT_PCRSM
    XS_AC97CTRL_STAT_SCRSM,   // XS_AC97CTRL_INT_SCRSM
    XS_AC97CTRL_STAT_SDONE,   // XS_AC97CTRL_INT_SDONE
    XS_AC97CTRL_STAT_CDONE    // XS_AC97CTRL_INT_CDONE

}; // XsAc97CtrlIntToStatusTransTbl[]
*/
extern XsAc97CtrlRegsT *XsAc97CtrlRegsP;
// XsAc97CtrlRegsT *XsAc97CtrlRegsP = (XsAc97CtrlRegsT *) XS_AC97CTRL_REGISTER_BASE;
 
                                
UINT32 XsAc97CtrlClearStatus (XsAc97CtrlStatusIdT);                                

UINT32 XsAc97CtrlRangeCheckStatusId (XsAc97CtrlStatusIdT);

static
void XsAc97CtrlSetStatusEntry ( XsAc97CtrlStatusEntryT* targetEntryP,
                                BOOL,
                                VUINT32*,
                                INT,
                                UINT32,
                                INT,
                                VUINT32*,
                                INT);


void XsAc97CtrlSWInit (void);
UINT32 XsAc97CtrlHWSetup (void);

UINT32 XsAc97CtrlWriteCodecReg   (XsAc97CtrlCodecModemIdT  ac97DeviceId, 
                                 AC97MixerRegisterIdT     targetRegister,
                                 UINT32                   newValue);
void playpcm(void);
#endif // #ifndef _XSAC97CTRL_H