library ieee;
use ieee.std_logic_1164.all;

entity ctrl	is
port(clk	:in	std_logic;
	 sel	:in std_logic;
	 set    :in	std_logic;
	 clkout :out std_logic);
end ctrl;

architecture one of ctrl is
begin
clkout <= (clk and sel) or ((not sel) and set);
end one;