?? top.rpt
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_X005 = EXP(!_LC017 & !_LC024 & _LC033 & _LC035 & !_LC064);
_X006 = EXP(!_LC009 & _LC017 & !_LC024 & !_LC033 & !_LC035);
_X007 = EXP(!_LC006 & !_LC017 & !_LC024 & _LC033 & !_LC035);
_X008 = EXP(!_LC017 & !_LC018 & !_LC024 & !_LC033 & _LC035);
_X009 = EXP(!ALE & !_LC017 & !_LC024 & !_LC033 & !_LC035);
_X010 = EXP(!_LC006 & !_LC010 & !_LC024 & _LC033 & !_LC060 & !_LC064);
_X011 = EXP(!ALE & !_LC009 & !_LC012 & !_LC018 & !_LC024 & !_LC033);
-- Node name is 'CK_out'
-- Equation name is 'CK_out', location is LC003, type is output.
CK_out = LCELL( _LC029 $ GND);
-- Node name is 'CK_out~fit~in1'
-- Equation name is 'CK_out~fit~in1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ029 $ VCC);
_EQ029 = !_LC024 & _X012 & _X013 & _X014 & _X015 & _X016 & _X017 &
_X018 & _X019;
_X012 = EXP(!_LC017 & _LC033 & _LC035 & _LC064);
_X013 = EXP( _LC017 & _LC033 & _LC035 & _LC060);
_X014 = EXP( _LC012 & _LC017 & !_LC033 & _LC035);
_X015 = EXP( _LC010 & _LC017 & _LC033 & !_LC035);
_X016 = EXP(!_LC017 & _LC018 & !_LC033 & _LC035);
_X017 = EXP( _LC006 & !_LC017 & _LC033 & !_LC035);
_X018 = EXP( _LC009 & _LC017 & !_LC033 & !_LC035);
_X019 = EXP( ALE & !_LC017 & !_LC033 & !_LC035);
-- Node name is 'P00' = '|74273b:18|Q1'
-- Equation name is 'P00', type is bidir
P00 = TRI(_LC024, _LC025);
_LC024 = DFFE( P00 $ GND, _EQ030, VCC, VCC, VCC);
_EQ030 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'P01' = '|74273b:18|Q2'
-- Equation name is 'P01', type is bidir
P01 = TRI(_LC021, _LC025);
_LC021 = DFFE( P01 $ GND, _EQ031, VCC, VCC, VCC);
_EQ031 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'P02' = '|74273b:18|Q3'
-- Equation name is 'P02', type is bidir
P02 = TRI(_LC020, _LC025);
_LC020 = DFFE( P02 $ GND, _EQ032, VCC, VCC, VCC);
_EQ032 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'P03' = '|74273b:18|Q4'
-- Equation name is 'P03', type is bidir
P03 = TRI(_LC019, _LC025);
_LC019 = DFFE( P03 $ GND, _EQ033, VCC, VCC, VCC);
_EQ033 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'P04' = '|74273b:18|Q5'
-- Equation name is 'P04', type is bidir
P04 = TRI(_LC017, _LC025);
_LC017 = DFFE( P04 $ GND, _EQ034, VCC, VCC, VCC);
_EQ034 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'P05' = '|74273b:18|Q6'
-- Equation name is 'P05', type is bidir
P05 = TRI(_LC033, _LC025);
_LC033 = DFFE( P05 $ GND, _EQ035, VCC, VCC, VCC);
_EQ035 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'P06' = '|74273b:18|Q7'
-- Equation name is 'P06', type is bidir
P06 = TRI(_LC035, _LC025);
_LC035 = DFFE( P06 $ GND, _EQ036, VCC, VCC, VCC);
_EQ036 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'P07' = '|74273b:18|Q8'
-- Equation name is 'P07', type is bidir
P07 = TRI(_LC036, _LC025);
_LC036 = DFFE( P07 $ GND, _EQ037, VCC, VCC, VCC);
_EQ037 = _X020;
_X020 = EXP( A15 & !_LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !WR);
-- Node name is 'RAM_RD'
-- Equation name is 'RAM_RD', location is LC030, type is output.
RAM_RD = LCELL( _EQ038 $ VCC);
_EQ038 = A15 & !_LC022 & !_LC026 & _LC027 & _LC028 & !_LC056 & !RD;
-- Node name is 'STATE_out' = ':37'
-- Equation name is 'STATE_out', type is output
STATE_out = DFFE( GND $ VCC, _EQ039, _LC021, VCC, VCC);
_EQ039 = AD0 & AD1 & AD2 & AD3 & AD4 & AD5 & AD6 & AD7 & AD8 &
AD9 & AD10 & AD11 & AD12 & AD13 & AD14;
-- Node name is '|div_clk:54|count0' from file "div_clk.tdf" line 8, column 7
-- Equation name is '_LC009', type is buried
_LC009 = TFFE( VCC, ALE, VCC, VCC, VCC);
-- Node name is '|div_clk:54|count1' from file "div_clk.tdf" line 8, column 7
-- Equation name is '_LC006', type is buried
_LC006 = TFFE( _LC009, ALE, VCC, VCC, VCC);
-- Node name is '|div_clk:54|count2' from file "div_clk.tdf" line 8, column 7
-- Equation name is '_LC010', type is buried
_LC010 = TFFE( _EQ040, ALE, VCC, VCC, VCC);
_EQ040 = _LC006 & _LC009;
-- Node name is '|div_clk:54|count3' from file "div_clk.tdf" line 8, column 7
-- Equation name is '_LC018', type is buried
_LC018 = TFFE( _EQ041, ALE, VCC, VCC, VCC);
_EQ041 = _LC006 & _LC009 & _LC010;
-- Node name is '|div_clk:54|count4' from file "div_clk.tdf" line 8, column 7
-- Equation name is '_LC012', type is buried
_LC012 = TFFE( _EQ042, ALE, VCC, VCC, VCC);
_EQ042 = _LC006 & _LC009 & _LC010 & _LC018;
-- Node name is '|div_clk:54|count5' from file "div_clk.tdf" line 8, column 7
-- Equation name is '_LC064', type is buried
_LC064 = TFFE( _EQ043, ALE, VCC, VCC, VCC);
_EQ043 = _LC006 & _LC009 & _LC010 & _LC012 & _LC018;
-- Node name is '|div_clk:54|count6' from file "div_clk.tdf" line 8, column 7
-- Equation name is '_LC060', type is buried
_LC060 = TFFE( _EQ044, ALE, VCC, VCC, VCC);
_EQ044 = _LC006 & _LC009 & _LC010 & _LC012 & _LC018 & _LC064;
-- Node name is '|mcu_ctrl:21|74373:112|:12'
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( _EQ045 $ GND);
_EQ045 = ALE & P00
# _LC022 & P00
# !ALE & _LC022;
-- Node name is '|mcu_ctrl:21|74373:112|:13'
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( _EQ046 $ GND);
_EQ046 = ALE & P01
# _LC028 & P01
# !ALE & _LC028;
-- Node name is '|mcu_ctrl:21|74373:112|:14'
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( _EQ047 $ GND);
_EQ047 = ALE & P02
# _LC027 & P02
# !ALE & _LC027;
-- Node name is '|mcu_ctrl:21|74373:112|:15'
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( _EQ048 $ GND);
_EQ048 = ALE & P03
# _LC026 & P03
# !ALE & _LC026;
-- Node name is '|mcu_ctrl:21|74373:112|:16'
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( _EQ049 $ GND);
_EQ049 = ALE & P04
# _LC056 & P04
# !ALE & _LC056;
-- Node name is '|74273b:18|~12~1' = '|74273b:18|Q8~1'
-- Equation name is '_LC025', type is buried
-- synthesized logic cell
_LC025 = LCELL( _EQ050 $ GND);
_EQ050 = A15 & _LC022 & !_LC026 & _LC027 & !_LC028 & !_LC056 & !RD;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, C, D
-- _X002 occurs in LABs A, C, D
-- _X003 occurs in LABs A, C, D
-- _X004 occurs in LABs A, C, D
-- _X005 occurs in LABs A, C, D
-- _X006 occurs in LABs A, C, D
-- _X007 occurs in LABs A, C, D
-- _X008 occurs in LABs A, C, D
-- _X009 occurs in LABs A, C, D
-- _X010 occurs in LABs A, C, D
-- _X011 occurs in LABs A, C, D
-- _X020 occurs in LABs B, C
Project Information d:\fast_adc\top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,984K
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