?? cy62256vso.sim.rpt
字號:
Simulator report for CY62256VSO
Thu Jan 08 17:20:24 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Simulator Summary
3. Simulator Settings
4. Simulation Waveforms
5. Coverage Summary
6. Complete 1/0-Value Coverage
7. Missing 1-Value Coverage
8. Missing 0-Value Coverage
9. Simulator INI Usage
10. Simulator Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------+
; Simulator Summary ;
+-----------------------------+-----------------+
; Type ; Value ;
+-----------------------------+-----------------+
; Simulation Start Time ; 0 ps ;
; Simulation End Time ; 20.0 us ;
; Simulation Netlist Size ; 105 nodes ;
; Simulation Coverage ; 28.74 % ;
; Total Number of Transitions ; 3910 ;
; Simulation Breakpoints ; 0 ;
; Family ; MAX3000A ;
; Device ; EPM3512AQC208-7 ;
+-----------------------------+-----------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Simulation mode ; Timing ; Timing ;
; Start time ; 0 ns ; 0 ns ;
; Simulation results format ; CVWF ; ;
; Add pins automatically to simulation output waveforms ; On ; On ;
; Check outputs ; Off ; Off ;
; Report simulation coverage ; On ; On ;
; Display complete 1/0 value coverage report ; On ; On ;
; Display missing 1-value coverage report ; On ; On ;
; Display missing 0-value coverage report ; On ; On ;
; Detect setup and hold time violations ; Off ; Off ;
; Detect glitches ; Off ; Off ;
; Disable timing delays in Timing Simulation ; Off ; Off ;
; Generate Signal Activity File ; Off ; Off ;
; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
; Group bus channels in simulation results ; Off ; Off ;
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
+--------------------------------------------------------------------------------------------+------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 28.74 % ;
; Total nodes checked ; 105 ;
; Total output ports checked ; 87 ;
; Total output ports with complete 1/0-value coverage ; 25 ;
; Total output ports with no 1/0-value coverage ; 60 ;
; Total output ports with no 1-value coverage ; 60 ;
; Total output ports with no 0-value coverage ; 62 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+-----------------------+------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------+------------------------------+------------------+
; |CY62256VSO|GLBCLK ; |CY62256VSO|GLBCLK~corein ; dataout ;
; |CY62256VSO|DATA[0] ; |CY62256VSO|DATA[0]~32 ; dataout ;
; |CY62256VSO|DATA[1] ; |CY62256VSO|DATA[1]~31 ; dataout ;
; |CY62256VSO|DATA[2] ; |CY62256VSO|DATA[2]~30 ; dataout ;
; |CY62256VSO|DATA[3] ; |CY62256VSO|DATA[3]~29 ; dataout ;
; |CY62256VSO|DATA[4] ; |CY62256VSO|DATA[4]~28 ; dataout ;
; |CY62256VSO|DATA[5] ; |CY62256VSO|DATA[5]~27 ; dataout ;
; |CY62256VSO|DATA[6] ; |CY62256VSO|DATA[6]~26 ; dataout ;
; |CY62256VSO|DATA[7] ; |CY62256VSO|DATA[7]~25 ; dataout ;
; |CY62256VSO|FPGADT[0] ; |CY62256VSO|FPGADT[0]~31 ; dataout ;
; |CY62256VSO|FPGADT[0] ; |CY62256VSO|FPGADT[0]~output ; padio ;
; |CY62256VSO|FPGADT[1] ; |CY62256VSO|FPGADT[1]~30 ; dataout ;
; |CY62256VSO|FPGADT[1] ; |CY62256VSO|FPGADT[1]~output ; padio ;
; |CY62256VSO|FPGADT[2] ; |CY62256VSO|FPGADT[2]~29 ; dataout ;
; |CY62256VSO|FPGADT[2] ; |CY62256VSO|FPGADT[2]~output ; padio ;
; |CY62256VSO|FPGADT[3] ; |CY62256VSO|FPGADT[3]~28 ; dataout ;
; |CY62256VSO|FPGADT[3] ; |CY62256VSO|FPGADT[3]~output ; padio ;
; |CY62256VSO|FPGADT[4] ; |CY62256VSO|FPGADT[4]~27 ; dataout ;
; |CY62256VSO|FPGADT[4] ; |CY62256VSO|FPGADT[4]~output ; padio ;
; |CY62256VSO|FPGADT[5] ; |CY62256VSO|FPGADT[5]~26 ; dataout ;
; |CY62256VSO|FPGADT[5] ; |CY62256VSO|FPGADT[5]~output ; padio ;
; |CY62256VSO|FPGADT[6] ; |CY62256VSO|FPGADT[6]~25 ; dataout ;
; |CY62256VSO|FPGADT[6] ; |CY62256VSO|FPGADT[6]~output ; padio ;
; |CY62256VSO|FPGADT[7] ; |CY62256VSO|FPGADT[7]~24 ; dataout ;
; |CY62256VSO|FPGADT[7] ; |CY62256VSO|FPGADT[7]~output ; padio ;
+-----------------------+------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-----------------------------+---------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------------+---------------------------------+------------------+
; |CY62256VSO|FPGAADDR[0]~30 ; |CY62256VSO|FPGAADDR[0]~30 ; dataout ;
; |CY62256VSO|FPGAADDR[1]~32 ; |CY62256VSO|FPGAADDR[1]~32 ; dataout ;
; |CY62256VSO|FPGAADDR[2]~34 ; |CY62256VSO|FPGAADDR[2]~34 ; dataout ;
; |CY62256VSO|FPGAADDR[3]~36 ; |CY62256VSO|FPGAADDR[3]~36 ; dataout ;
; |CY62256VSO|FPGAADDR[4]~38 ; |CY62256VSO|FPGAADDR[4]~38 ; dataout ;
; |CY62256VSO|FPGAADDR[5]~40 ; |CY62256VSO|FPGAADDR[5]~40 ; dataout ;
; |CY62256VSO|FPGAADDR[6]~42 ; |CY62256VSO|FPGAADDR[6]~42 ; dataout ;
; |CY62256VSO|FPGAADDR[7]~44 ; |CY62256VSO|FPGAADDR[7]~44 ; dataout ;
; |CY62256VSO|FPGAADDR[8]~46 ; |CY62256VSO|FPGAADDR[8]~46 ; dataout ;
; |CY62256VSO|FPGAADDR[9]~48 ; |CY62256VSO|FPGAADDR[9]~48 ; dataout ;
; |CY62256VSO|FPGAADDR[10]~50 ; |CY62256VSO|FPGAADDR[10]~50 ; dataout ;
; |CY62256VSO|FPGAADDR[11]~52 ; |CY62256VSO|FPGAADDR[11]~52 ; dataout ;
; |CY62256VSO|FPGAADDR[12]~54 ; |CY62256VSO|FPGAADDR[12]~54 ; dataout ;
; |CY62256VSO|FPGAADDR[13]~56 ; |CY62256VSO|FPGAADDR[13]~56 ; dataout ;
; |CY62256VSO|FPGAADDR[14]~58 ; |CY62256VSO|FPGAADDR[14]~58 ; dataout ;
; |CY62256VSO|RD~reg0 ; |CY62256VSO|RD~reg0 ; dataout ;
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