?? dds.map.rpt
字號:
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------+
; cos_rom.tdf ; yes ; User AHDL File ; F:/fpga test/dds/cos_rom.tdf ;
; mux4.tdf ; yes ; User AHDL File ; F:/fpga test/dds/mux4.tdf ;
; ram.tdf ; yes ; User AHDL File ; F:/fpga test/dds/ram.tdf ;
; sin_rom.tdf ; yes ; User AHDL File ; F:/fpga test/dds/sin_rom.tdf ;
; square.tdf ; yes ; User AHDL File ; F:/fpga test/dds/square.tdf ;
; dds.bdf ; yes ; User Block Diagram/Schematic File ; F:/fpga test/dds/dds.bdf ;
; altsyncram.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/altsyncram.inc ;
; lpm_mux.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/lpm_mux.inc ;
; lpm_mux.tdf ; yes ; Megafunction ; f:/altera/quartus60/libraries/megafunctions/lpm_mux.tdf ;
; aglobal60.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/aglobal60.inc ;
; muxlut.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/muxlut.inc ;
; bypassff.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/altshift.inc ;
; db/mux_ogc.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/mux_ogc.tdf ;
; altsyncram.tdf ; yes ; Megafunction ; f:/altera/quartus60/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_decode.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/lpm_decode.inc ;
; a_rdenreg.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_vpl1.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/altsyncram_vpl1.tdf ;
; db/altsyncram_b431.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/altsyncram_b431.tdf ;
; db/altsyncram_ut41.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/altsyncram_ut41.tdf ;
; db/altsyncram_4pi2.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/altsyncram_4pi2.tdf ;
; sld_mod_ram_rom.vhd ; yes ; Encrypted Megafunction ; f:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; f:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd ;
; db/altsyncram_3u41.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/altsyncram_3u41.tdf ;
; db/altsyncram_9pi2.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/altsyncram_9pi2.tdf ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; f:/altera/quartus60/libraries/megafunctions/sld_hub.vhd ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; f:/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf ;
; lpm_constant.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/lpm_constant.inc ;
; dffeea.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/dffeea.inc ;
; lpm_decode.tdf ; yes ; Megafunction ; f:/altera/quartus60/libraries/megafunctions/lpm_decode.tdf ;
; declut.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/declut.inc ;
; lpm_compare.inc ; yes ; Other ; f:/altera/quartus60/libraries/megafunctions/lpm_compare.inc ;
; db/decode_ogi.tdf ; yes ; Auto-Generated Megafunction ; F:/fpga test/dds/db/decode_ogi.tdf ;
; sld_dffex.vhd ; yes ; Encrypted Megafunction ; f:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------+
+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------------+
; Total logic elements ; 275 ;
; -- Combinational with no register ; 109 ;
; -- Register only ; 28 ;
; -- Combinational with a register ; 138 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 99 ;
; -- 3 input functions ; 77 ;
; -- 2 input functions ; 69 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 1 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 243 ;
; -- arithmetic mode ; 32 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 53 ;
; -- asynchronous clear/load mode ; 94 ;
; ; ;
; Total registers ; 166 ;
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