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--     design files limited to Xilinx devices or technologies. Use            --
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-- You must compile the wrapper file add8_nc.vhd when simulating
-- the core, add8_nc. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY add8_nc IS
  port (
  A: IN std_logic_VECTOR(11 downto 0);
  B: IN std_logic_VECTOR(11 downto 0);
  Q_C_OUT: OUT std_logic;
  ADD: IN std_logic;
  Q: OUT std_logic_VECTOR(11 downto 0);
  CLK: IN std_logic;
  ACLR: IN std_logic);
END add8_nc;

ARCHITECTURE add8_nc_a OF add8_nc IS

component wrapped_add8_nc
  port (
  A: IN std_logic_VECTOR(11 downto 0);
  B: IN std_logic_VECTOR(11 downto 0);
  Q_C_OUT: OUT std_logic;
  ADD: IN std_logic;
  Q: OUT std_logic_VECTOR(11 downto 0);
  CLK: IN std_logic;
  ACLR: IN std_logic);
end component;

-- Configuration specification 
  for all : wrapped_add8_nc use entity XilinxCoreLib.C_ADDSUB_V6_0(behavioral)    generic map(
      c_has_bypass_with_cin => 0,
      c_a_type => 1,
      c_has_sclr => 0,
      c_has_b_out => 0,
      c_sync_priority => 1,
      c_has_aset => 0,
      c_has_s => 0,
      c_has_q => 1,
      c_bypass_enable => 0,
      c_b_constant => 0,
      c_has_ovfl => 0,
      c_high_bit => 11,
      c_latency => 1,
      c_sinit_val => "0",
      c_has_bypass => 0,
      c_pipe_stages => 1,
      c_has_sset => 0,
      c_has_ainit => 0,
      c_has_a_signed => 0,
      c_has_q_c_out => 1,
      c_b_type => 1,
      c_has_add => 1,
      c_has_sinit => 0,
      c_has_b_in => 0,
      c_has_b_signed => 0,
      c_bypass_low => 0,
      c_b_value => "0",
      c_enable_rlocs => 1,
      c_add_mode => 2,
      c_has_aclr => 1,
      c_out_width => 12,
      c_low_bit => 0,
      c_ainit_val => "0000",
      c_has_q_ovfl => 0,
      c_has_q_b_out => 0,
      c_has_c_out => 0,
      c_b_width => 12,
      c_a_width => 12,
      c_sync_enable => 0,
      c_has_ce => 0,
      c_has_c_in => 0);
BEGIN

U0 : wrapped_add8_nc
    port map (
      A => A,
      B => B,
      Q_C_OUT => Q_C_OUT,
      ADD => ADD,
      Q => Q,
      CLK => CLK,
      ACLR => ACLR);
END add8_nc_a;

-- synopsys translate_on