?? ata_includes.h
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/*********************************************************************
(c) copyright Freescale Semiconductor Hong Kong Ltd 2004
ALL RIGHTS RESERVED
*********************************************************************
ATA Driver Module for S12 MCUs
*********************************************************************
File: ata_includes.h
Description: Define my System Configuration & Compiler Options.
Date: Jul. 2002
Author: Derek Lau
********************************************************************/
#ifndef _ATA_INTRN_GLOBAL_DECL_
#define _ATA_INTRN_GLOBAL_DECL_ extern
#endif
#ifndef _H_ATA_INCLUDES_ // To avoid multiple defining
#define _H_ATA_INCLUDES_ // start of Constants & Macros definition
#include "Hidef.h"
// ======================================================
//
// Register Definition for ATA5HC Module
//
// ======================================================
#define ATA_HCFG *(volatile muint16*)(ATA_BASE+0x00) /* Host Configuration Register */
#define ATA_HCFG_H *(volatile muint8*)(ATA_BASE+0x00) /* High register */
#define ATASMR 7 // State Machine Reset
#define ATAFR 6 // FIFO Reset
#define ATACLKEN 3 // clock enable
#define ATAXNW 2 // IPS_XFR_WAIT
#define ATAIE 1 // Interrupt Enable
#define ATAIORDY 0 // Enable I/O ready function
#define ATA_HCFG_L *(volatile muint8*)(ATA_BASE+0x01) /* Low register */
#define ATA_HSR *(volatile muint16*)(ATA_BASE+0x02) /* Host Status Register */
#define ATA_HSR_H *(volatile muint8*)(ATA_BASE+0x02) /* High register */
#define ATATIP 7 // Transfer in progress
#define ATAUREP 6 // UDMA read extended pause
#define ATADRAB 5 // Device Register Access Busy
#define ATARERR 1 // Read on unimplemented register
#define ATAWERR 0 // Write on unimplemented register
#define ATA_HSR_L *(volatile muint8*)(ATA_BASE+0x03) /* High register */
#define ATA_RAS 0 // Register Access Status
#define ATA_PIO1 *(volatile muint16*)(ATA_BASE+0x04) /* PIO Timing Register 1 */
#define ATA_PIO_T0 *(volatile muint8*)(ATA_BASE+0x04) /* t0 */
#define ATA_PIO_2_8 *(volatile muint8*)(ATA_BASE+0x05) /* t2 for 8 bit xfer */
#define ATA_PIO2 *(volatile muint16*)(ATA_BASE+0x06) /* PIO Timing Register 2 */
#define ATA_PIO_T2_16 *(volatile muint8*)(ATA_BASE+0x06) /* t2 for 16 bit xfer */
#define ATA_PIO_T2I *(volatile muint8*)(ATA_BASE+0x07) /* t2i DIOR#/DIOW recovery time */
#define ATA_PIO3 *(volatile muint16*)(ATA_BASE+0x08) /* PIO Timing Register Register 3*/
#define ATA_PIO_T4 *(volatile muint8*)(ATA_BASE+0x08) /* t4 PIO write (DIOW#) data hold time */
#define ATA_PIO_T1 *(volatile muint8*)(ATA_BASE+0x09) /* t1 adddress valid to R#/W# setup */
#define ATA_PIO4 *(volatile muint16*)(ATA_BASE+0x0A) /* PIO Timing Register 4 */
#define ATA_PIO4_B *(volatile muint8*)(ATA_BASE+0x0A) /* PIO Timing Register 4 (byte)*/
#define ATA_PIO_TA *(volatile muint8*)(ATA_BASE+0x0A) /* tA single cycle ipg_clk */
#define ATA_DMA1 *(volatile muint16*)(ATA_BASE+0x0C) /* DMA Timing Register 1 */
#define ATA_DMA_T0 *(volatile muint8*)(ATA_BASE+0x0C) /* t0 cycle time for multiword DMA*/
#define ATA_DMA_TD *(volatile muint8*)(ATA_BASE+0x0D) /* tD DIOR#/DORW# asserted pulse width */
#define ATA_DMA2 *(volatile muint16*)(ATA_BASE+0x0E) /* DMA Timing Register 2 */
#define ATA_DMA_TK *(volatile muint8*)(ATA_BASE+0x0E) /* tK DIOR#/DIOW# negated pulse width */
#define ATA_DMA_TM *(volatile muint8*)(ATA_BASE+0x0F) /* tM CS0#,CS1# valid to DIOR#/DIOW# */
#define ATA_DMA3 *(volatile muint16*)(ATA_BASE+0x10) /* DMA Timing Register 3 */
#define ATA_DMA_TH *(volatile muint8*)(ATA_BASE+0x10) /* DIOW# data hold time */
#define ATA_DMA_TJ *(volatile muint8*)(ATA_BASE+0x11) /* DIOR#/DIOW# to DMACK# hold */
#define ATA_DMA4 *(volatile muint16*)(ATA_BASE+0x12) /* DMA Timing Register 4 */
#define ATA_DMA4_B *(volatile muint8*)(ATA_BASE+0x12) /* DMA Timing Register 4 (byte)*/
#define ATA_DMA_TN *(volatile muint8*)(ATA_BASE+0x12) /* CS0#,CS1# hold time */
#define ATA_UDMA1 *(volatile muint16*)(ATA_BASE+0x14) /* UDMA Timing Register 1 */
#define ATA_UDMA_T2CYCTYP *(volatile muint8*)(ATA_BASE+0x14) /* average two cycle time */
#define ATA_UDMA_TCYC *(volatile muint8*)(ATA_BASE+0x15) /* strobe edge to strobe edge cycle */
#define ATA_UDMA2 *(volatile muint16*)(ATA_BASE+0x16) /* UDMA Timing Register 2 */
#define ATA_UDMA_TDS *(volatile muint8*)(ATA_BASE+0x16) /* Read data setup time */
#define ATA_UDMA_TDH *(volatile muint8*)(ATA_BASE+0x17) /* Read data hold time */
#define ATA_UDMA3 *(volatile muint16*)(ATA_BASE+0x18) /* UDMA Timing Register 3 */
#define ATA_UDMA_TDVS *(volatile muint8*)(ATA_BASE+0x18) /* Write data setup time */
#define ATA_UDMA_TDVH *(volatile muint8*)(ATA_BASE+0x19) /* Write data hold time */
#define ATA_UDMA4 *(volatile muint16*)(ATA_BASE+0x1A) /* UDMA Timing Register 4 */
#define ATA_UDMA_TFS *(volatile muint8*)(ATA_BASE+0x1A) /* First strobe time */
#define ATA_UDMA_TLI *(volatile muint8*)(ATA_BASE+0x1B) /* Limited interlock time (def max) */
#define ATA_UDMA5 *(volatile muint16*)(ATA_BASE+0x1C) /* UDMA Timing Register 5 */
#define ATA_UDMA_TML1 *(volatile muint8*)(ATA_BASE+0x1C) /* Limited interlock time (def min) */
#define ATA_UDMA_TAZ *(volatile muint8*)(ATA_BASE+0x1D) /* max time release from being driven */
#define ATA_UDMA6 *(volatile muint16*)(ATA_BASE+0x1E) /* UDMA Timing Register 6 */
#define ATA_UDMA_TENV *(volatile muint8*)(ATA_BASE+0x1E) /* DMACK# to STOP and HDMARDY# */
#define ATA_UDMA_TSR *(volatile muint8*)(ATA_BASE+0x1F) /* Strobe to DMARDY */
#define ATA_UDMA7 *(volatile muint16*)(ATA_BASE+0x20) /* UDMA Timing Register 7 */
#define ATA_UDMA_TSS *(volatile muint8*)(ATA_BASE+0x20) /* Strobe to negation of DMARQ */
#define ATA_UDMA_TRFS *(volatile muint8*)(ATA_BASE+0x21) /* Ready to final strobe time */
#define ATA_UDMA8 *(volatile muint16*)(ATA_BASE+0x22) /* UDMA Timing Register 8 */
#define ATA_UDMA_TRP *(volatile muint8*)(ATA_BASE+0x22) /* Ready to pause time */
#define ATA_UDMA_TACK *(volatile muint8*)(ATA_BASE+0x23) /* Setup and hold time for DMACK# */
#define ATA_UDMA9 *(volatile muint16*)(ATA_BASE+0x24) /* UDMA Timing Register 9 */
#define ATA_UDMA9_B *(volatile muint8*)(ATA_BASE+0x24) /* UDMA Timing Register 9 (byte) */
#define ATA_UDMA_TZAH *(volatile muint8*)(ATA_BASE+0x24) /* Strobe to negation of DMARQ */
#define ATA_DCTR *(volatile muint16*)(ATA_BASE+0x2E) /* Device Control Register */
#define ATA_DCTR_B *(volatile muint8*)(ATA_BASE+0x2E) /* Device Control Register (byte)*/
#define ATAHOB 7 // high order byte
#define ATASRST 2 // Host controlled software reset
#define ATANIEN 1 // Host controlled interrupt disable
#define ATAHCIDIS 1 // same as above
#define ATAZERO 0 // must be zero
#define ATA_DASR *(volatile muint16*)(ATA_BASE+0x2E) /* Alternate Status Register */
#define ATA_DASR_B *(volatile muint8*)(ATA_BASE+0x2E) /* Alternate Status Register (byte)*/
#define ATABSY 7 // Device busy
#define ATADRDY 6 // Device ready
#define ATADF 5 // Device fault
// #define ATADMARDY 5 // DMA Ready
#define ATADRQ 3 // Device ready to xfer a word
#define ATAERR 0 // Error
#define ATA_DDR *(volatile muint16*)(ATA_BASE+0x30) /* Data Register */
#define ATA_DDR_H *(volatile muint8*)(ATA_BASE+0x30) /* High Register */
#define ATA_DDR_L *(volatile muint8*)(ATA_BASE+0x31) /* Low Register */
#define ATA_DFR *(volatile muint16*)(ATA_BASE+0x32) /* Feature Register */
#define ATA_DFR_B *(volatile muint8*)(ATA_BASE+0x32) /* Feature Register (byte) */
#define ATA_DER *(volatile muint16*)(ATA_BASE+0x32) /* Error Register */
#define ATA_DER_B *(volatile muint8*)(ATA_BASE+0x32) /* Error Register (byte)*/
#define ATAICRC 7 // CRC error
#define ATAUNC 6 // uncorrectable data
#define ATAMC 5 // media in a removable device changed
#define ATAIDNF 4 // user-accessible address not found
#define ATAMCR 3 // media change request detected
#define ATAABRT 2 // Command abort
#define ATANM 1 // no media is present
#define ATA_DSCR *(volatile muint16*)(ATA_BASE+0x34) /* Drive Sector Count Register */
#define ATA_DSCR_B *(volatile muint8*)(ATA_BASE+0x34) /* Drive Sector Count Register (byte) */
#define ATA_DSNR *(volatile muint16*)(ATA_BASE+0x36) /* Drive Sector Number Register */
#define ATA_DSNR_B *(volatile muint8*)(ATA_BASE+0x36) /* Drive Sector Number Register (byte) */
#define ATA_LBAL *(volatile muint16*)(ATA_BASE+0x36) /* ATA6 LBA Low Register */
#define ATA_LBAL_B *(volatile muint8*)(ATA_BASE+0x36) /* ATA6 LBA Low Register (byte) */
#define ATA_DCLR *(volatile muint16*)(ATA_BASE+0x38) /* Drive Cyliner Low Register */
#define ATA_DCLR_B *(volatile muint8*)(ATA_BASE+0x38) /* Drive Cyliner Low Register (byte) */
#define ATA_LBAM *(volatile muint16*)(ATA_BASE+0x38) /* ATA6 LBA Mid Register */
#define ATA_LBAM_B *(volatile muint8*)(ATA_BASE+0x38) /* ATA6 LBA Mid Register (byte) */
#define ATA_DCHR *(volatile muint16*)(ATA_BASE+0x3A) /* Drive Cyliner High Register */
#define ATA_DCHR_B *(volatile muint8*)(ATA_BASE+0x3A) /* Drive Cyliner High Register (byte) */
#define ATA_DCHR_L *(volatile muint8*)(ATA_BASE+0x3B) /* Drive Cyliner High Register (byte) */
#define ATA_LBAH *(volatile muint16*)(ATA_BASE+0x3A) /* ATA6 LBA High Register */
#define ATA_LBAH_B *(volatile muint8*)(ATA_BASE+0x3A) /* ATA6 LBA High Register (byte) */
#define ATA_DDHR *(volatile muint16*)(ATA_BASE+0x3C) /* Drive Device/Head Register */
#define ATA_DDHR_B *(volatile muint8 *)(ATA_BASE+0x3C) /* Drive Device/Head Register (byte) */
#define ATA_DCR *(volatile muint16*)(ATA_BASE+0x3E) /* Drive Command Register */
#define ATA_DCR_H *(volatile muint8*)(ATA_BASE+0x3E) /* Drive Command Register (byte) */
#define ATA_DSR *(volatile muint16*)(ATA_BASE+0x3E) /* Drive Status Register */
#define ATA_DSR_B *(volatile muint8*)(ATA_BASE+0x3E) /* Drive Status Register (byte)*/
//Defined in Alternate Status Register
//#define ATA_BSY 7 // Device busy
//#define ATA_DRDY 6 // Device ready
//#define ATA_DF 5 // Device fault
//#define ATA_DRQ 3 // Device ready to xfer a word
//#define ATA_ERR 0 // Error
#define ATA_DCR_L *(volatile muint8*)(ATA_BASE+0x3F) /* Drive Status Register (byte)*/
#define ATAPIE 7 // pause interrupt enable
#define ATAHUT 6 // DMA burst terminate
#define ATAAR 5 // automatic FIFO reset
#define ATADCRFE 4 // FIFO flush
#define ATADMAIE 3 // DMA interrupt enable
#define ATAUDMA 2 // UDMA/DMA
#define ATAUDMARD 1 // DMA read
#define ATAUDMAWR 0 // DMA write
// =====================================================
//
// Module Specific Constant definitions
//
// =====================================================
#define kMaxNumberOfATAHook 4 // Max number of hooks per event
#define kBit15 0x8000
#define kBit14 0x4000
#define kBit13 0x2000
#define kBit12 0x1000
#define kBit11 0x0800
#define kBit10 0x0400
#define kBit9 0x0200
#define kBit8 0x0100
#define kBit7 0x0080
#define kBit6 0x0040
#define kBit5 0x0020
#define kBit4 0x0010
#define kBit3 0x0008
#define kBit2 0x0004
#define kBit1 0x0002
#define kBit0 0x0001
#define kMaskBit15 0x7FFF
#define kMaskBit14 0xBFFF
#define kMaskBit13 0xDFFF
#define kMaskBit12 0xEFFF
#define kMaskBit11 0xF7FF
#define kMaskBit10 0xFBFF
#define kMaskBit9 0xFDFF
#define kMaskBit8 0xFEFF
#define kMaskBit7 0x7F
#define kMaskBit6 0xBF
#define kMaskBit5 0xDF
#define kMaskBit4 0xEF
#define kMaskBit3 0xF7
#define kMaskBit2 0xFB
#define kMaskBit1 0xFD
#define kMaskBit0 0xFE
#define kOneByte 0x08
#define kTwoByte 0x10
#define kThreeByte 0x18
// =====================================================
//
// ATA/ATAPI constants
//
// =====================================================
#define kATACommandSize 8 //ATA Command size
// ATA Command Definiation (see ATA6r3 chapter 8, also pp.476 table E-2)
#define kATACmdNOP 0x00 // NOP
#define kATACmdReset 0x08 // device reset
#define kATACmdRead 0x20 // read sectors
#define kATACmdReadExt 0x24 // read ext
#define kATACmdReadDMAExt 0x25 // read DMA ext
#define kATACmdReadMaxAddExt 0x27 // read native max address ext
#define kATACmdWrite 0x30 // write sectors
#define kATACmdWriteDMAExt 0x35 // write DMA ext
#define kATACmdReadVerify 0x40 // read verify
#define kATACmdPacket 0xa0 // packet command
#define kATACmdIdentifyP 0xa1 // identify packet device
#define kATACmdService 0xa2 // service command
#define kATACmdReadMul 0xc4 // read multiple
#define kATACmdWriteMul 0xc5 // write multiple
#define kATACmdSetMul 0xc6 // set multiple mode
#define kATACmdReadDMAQ 0xc7 // read DMA QUEUED
#define kATACmdReadDMA 0xc8 // read DMA
#define kATACmdWriteDMA 0xca // write DMA
#define kATACmdWriteDMAQ 0xcc // write DMA QUEUED
#define kATACmdFfushCache 0xe7 // flush cache
#define kATACmdIdentify 0xec // identify device
#define kATACmdSetFeatures 0xef // set features
#define kATACmdReadMaxAdd 0xf8 // read native max address
// PACKET Command 0xA0
#define kATA_C_P_STATUS_CHong Kong 0x01
#define ATA_UDMA_MODE0 0x01
#define ATA_UDMA_MODE1 0x02
#define ATA_UDMA_MODE2 0x04
#define ATA_UDMA_MODE3 0x08
#define ATA_UDMA_MODE4 0x10
#define ATA_UDMA_MODE5 0x20
// ATA Set Feature 0xef sub commands (see ATA6r3 p.226 table 44)
#define kATAFCmdSetTransfer 0x03 // set transfer mode
#define kATAFCmdEnWriteCache 0x02 // enable write cache
#define kATAFCmdDisWriteCache 0x82 // disable write cache
#define kATAFCmdEnReadACache 0xaa // enable readahead cache
#define kATAFCmdDisReadACache 0x55 // disable readahead cache
#define kATAFCmdEnReleaseInt 0x5d // enable release interrupt
#define kATAFCmdDisReleaseInt 0xdd // disable release interrupt
#define kATAFCmdEnServiceInt 0x5e // enable service interrupt
#define kATAFCmdDisServiceInt 0xde // disable service interrupt
// ATA Set Feature sub command 0x03 SETXFER
#define kATAFCmdXfPIODefMode 0x00 // PIO default mode
#define kATAFCmdXfPIO0 0x08 // PIO mode 0
#define kATAFCmdXfPIO1 0x09 // PIO mode 1
#define kATAFCmdXfPIO2 0x0a // PIO mode 2
#define kATAFCmdXfPIO3 0x0b // PIO mode 3
#define kATAFCmdXfPIO4 0x0c // PIO mode 4
#define kATAFCmdXfMDMA0 0x20 // multi word DMA 2
#define kATAFCmdXfMDMA1 0x21 // multi word DMA 2
#define kATAFCmdXfMDMA2 0x22 // multi word DMA 2
#define kATAFCmdXfUDMA0 0x40 // UDMA mode 0
#define kATAFCmdXfUDMA1 0x41 // UDMA mode 1
#define kATAFCmdXfUDMA2 0x42 // UDMA mode 2
#define kATAFCmdXfUDMA3 0x43 // UDMA mode 3
#define kATAFCmdXfUDMA4 0x44 // UDMA mode 4
#define kATAFCmdXfUDMA5 0x45 // UDMA mode 5
// Identify [Packet] Device information
#define kATADevInfoGen 0 // b0=0/1 = 12/16 bit packet len
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