LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
ENTITY  sreg8  IS
    PORT(
         clk,load:IN STD_LOGIC;
              din:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               qb:OUT STD_LOGIC);
END  sreg8;

ARCHITECTURE  execute  OF sreg8  IS
  SIGNAL  reg8:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
      PROCESS(clk,load)
      BEGIN
          IF clk'EVENT AND clk='1'THEN
              IF load='1'THEN
              reg8<=din;
              ELSE
              reg8(6 DOWNTO 0)<=reg8(7 DOWNTO 1);
              END IF;
           END IF;
       END PROCESS;
    qb<=reg8(0);
END execute;