//******************************************************************************
//
//  Xilinx, Inc. 2002                 www.xilinx.com
//
//  XAPP 253 - Synthesizable DDR SDRAM Controller
//
//*******************************************************************************
//
//  File name :       infrastructure.v
//
//  Description :     
//                    Main fucntions of this module
//                       - generation of FPGA clocks.
//                       - generation of reset signals
//                       - implements calibration mechanism
//
//  Date - revision : 05/01/2002
//
//  Author :          Lakshmi Gopalakrishnan ( Modified by Sailaja) 
//
//  Contact : e-mail  hotline@xilinx.com
//            phone   + 1 800 255 7778 
//
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