--******************************************************************************
--
--  Xilinx, Inc. 2002                 www.xilinx.com
--
--  XAPP 253 - Synthesizable DDR SDRAM Controller
--
--*******************************************************************************
--
--  File name :       ddr2_top
--
--  Description :     
--                    Main DDR SDRAM controller block. This includes the following
--                    features:
--                    - The main controller state machine that controlls the 
--                    initialization process upon power up, as well as the 
--                    read, write, and refresh commands. 
--                    - handles the data path during READ and WRITEs.
--                    - Generates control signals for other modules, including the
--                      data strobe(DQS) signal
--
--  Date - revision : 05/01/2002
--
--  Author :          Lakshmi Gopalakrishnan ( Modified by Sailaja)
--
--  Contact : e-mail  hotline@xilinx.com
--            phone   + 1 800 255 7778 
--
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--              implied warranties of merchantability, non-infringement, or 
--              fitness for a particular purpose. Xilinx does not warrant that 
--              the functions contained in these designs will meet your 
--              requirements, or that the operation of these designs will be 
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--              will be corrected. Furthermore, Xilinx does not warrant or 
--              make any representations regarding use or the results of the 
--              use of the designs in terms of correctness, accuracy, 
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--
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