Release 9.2.03i par J.39Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.forever-s1::  Sun Dec 02 17:29:15 2007par -ol high -xe c -w mapped.ncd routed.ncd mapped.pcf INFO:Par:338 -    Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is   intended to be used for designs that are not meeting timing but where the   designer wants the tools to continue iterating on the design until no further   design speed improvements are possible.  This can result in very long   runtimes since the tools will continue improving the design even if the time   specs can not be met. If you are looking for the best possible design speed   available from a long but reasonable runtime use Extra Effort Level "n"ormal.    It will stop iterating on the design when the design speed improvements have   shrunk to the point that the time specs are not expected to be met.Constraints file: mapped.pcf.Loading device for application Rf_Device from file '5vlx50t.nph' in environment /program/ise92.   "xilinx_pci_exp_4_lane_ep" is an NCD, version 3.1, device xc5vlx50t, package ff1136, speed -1Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)Device speed data version:  "PRODUCTION 1.57 2007-08-28".INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.Device Utilization Summary:   Number of BUFDSs                          1 out of 6      16%   Number of BUFGs                           3 out of 32      9%   Number of DSP48Es                         1 out of 48      2%   Number of GTP_DUALs                       2 out of 6      33%      Number of LOCed GTP_DUALs              2 out of 2     100%   Number of External IOBs                   1 out of 480     1%      Number of LOCed IOBs                   1 out of 1     100%   Number of External IPADs                 10 out of 518     1%      Number of LOCed IPADs                  2 out of 10     20%   Number of External OPADs                  8 out of 24     33%      Number of LOCed OPADs                  0 out of 8       0%   Number of PCIEs                           1 out of 1     100%   Number of PLL_ADVs                        1 out of 6      16%   Number of RAMB36SDP_EXPs                  2 out of 60      3%      Number of LOCed RAMB36SDP_EXPs         1 out of 2      50%   Number of RAMB36_EXPs                     4 out of 60      6%      Number of LOCed RAMB36_EXPs            4 out of 4     100%   Number of Slice Registers              2892 out of 28800  10%      Number used as Flip Flops           2888      Number used as Latches                 4      Number used as LatchThrus              0   Number of Slice LUTS                   2794 out of 28800   9%   Number of Slice LUT-Flip Flop pairs    3889 out of 28800  13%Overall effort level (-ol):   High Router effort level (-rl):    High Starting initial Timing Analysis.  REAL time: 1 mins 11 secs Finished initial Timing Analysis.  REAL time: 1 mins 12 secs Starting RouterPhase 1: 20370 unrouted;       REAL time: 1 mins 15 secs Phase 2: 17282 unrouted;       REAL time: 1 mins 20 secs Phase 3: 6604 unrouted;       REAL time: 1 mins 48 secs Phase 4: 6604 unrouted; (1256798)      REAL time: 1 mins 49 secs Phase 5: 6922 unrouted; (118384)      REAL time: 3 mins 23 secs Phase 6: 6938 unrouted; (110644)      REAL time: 3 mins 25 secs Phase 7: 0 unrouted; (107856)      REAL time: 6 mins 45 secs Updating file: routed.ncd with current fully routed design.Phase 8: 0 unrouted; (107856)      REAL time: 7 mins 15 secs Phase 9: 0 unrouted; (107856)      REAL time: 7 mins 18 secs Phase 10: 0 unrouted; (107856)      REAL time: 9 mins 1 secs Phase 11: 0 unrouted; (0)      REAL time: 9 mins 11 secs Phase 12: 0 unrouted; (0)      REAL time: 9 mins 15 secs Total REAL time to Router completion: 9 mins 15 secs Total CPU time to Router completion: 9 mins 13 secs Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|           trn_clk_c |BUFGCTRL_X0Y11| No   | 1376 |  0.385     |  1.893      |+---------------------+--------------+------+------+------------+-------------+|ep/BU2/U0/pcie_ep0/p |              |      |      |            |             ||cie_blk/SIO/.pcie_gt |              |      |      |            |             ||_wrapper_i/icdrreset |              |      |      |            |             ||                 <0> |         Local|      |    1 |  0.000     |  0.451      |+---------------------+--------------+------+------+------------+-------------+|ep/BU2/U0/pcie_ep0/p |              |      |      |            |             ||cie_blk/SIO/.pcie_gt |              |      |      |            |             ||_wrapper_i/icdrreset |              |      |      |            |             ||                 <2> |         Local|      |    1 |  0.000     |  0.583      |+---------------------+--------------+------+------+------------+-------------+|ep/BU2/U0/pcie_ep0/p |              |      |      |            |             ||cie_blk/SIO/.pcie_gt |              |      |      |            |             ||_wrapper_i/icdrreset |              |      |      |            |             ||                 <3> |         Local|      |    1 |  0.000     |  0.624      |+---------------------+--------------+------+------+------------+-------------+|ep/BU2/U0/pcie_ep0/p |              |      |      |            |             ||cie_blk/SIO/.pcie_gt |              |      |      |            |             ||_wrapper_i/icdrreset |              |      |      |            |             ||                 <1> |         Local|      |    1 |  0.000     |  0.447      |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays.   The Delay Summary ReportThe NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        1.165   The MAXIMUM PIN DELAY IS:                               5.723   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.811   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00   ---------   ---------   ---------   ---------   ---------   ---------        8273        7428        1352         150          89           0Timing Score: 0Number of Timing Constraints that were not applied: 3Asterisk (*) preceding a constraint indicates it was not met.   This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing                                               |         |    Slack   | Achievable | Errors |    Score   ------------------------------------------------------------------------------------------------------  PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.000ns|     4.000ns|       0|           0  p0/pcie_blk/clocking_i/clkout0" derived f | HOLD    |     0.019ns|            |       0|           0  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |              50%                                       |         |            |            |        |            ------------------------------------------------------------------------------------------------------  PERIOD analysis for net "ep/BU2/U0/pcie_e | SETUP   |     0.000ns|     4.000ns|       0|           0  p0/pcie_blk/clocking_i/clkout0" derived f | HOLD    |     0.019ns|            |       0|           0  rom  NET "sys_clk_c" PERIOD = 10 ns HIGH  |         |            |            |        |              50%                                       |         |            |            |        |            ------------------------------------------------------------------------------------------------------  NET "sys_clk_c" PERIOD = 10 ns HIGH 50%   | N/A     |         N/A|         N/A|     N/A|         N/A------------------------------------------------------------------------------------------------------  TS_MGTCLK = PERIOD TIMEGRP "MGTCLK" 100 M | N/A     |         N/A|         N/A|     N/A|         N/A  Hz HIGH 50%                               |         |            |            |        |            ------------------------------------------------------------------------------------------------------  TS_ep_BU2_U0_pcie_ep0_pcie_blk_clocking_i | N/A     |         N/A|         N/A|     N/A|         N/A  _clkout0 = PERIOD TIMEGRP         "ep_BU2 |         |            |            |        |              _U0_pcie_ep0_pcie_blk_clocking_i_clkout0" |         |            |            |        |               TS_MGTCLK * 2.5 HIGH         50%         |         |            |            |        |            ------------------------------------------------------------------------------------------------------All constraints were met.INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the    constraint does not cover any paths or that it has no requested value.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 9 mins 23 secs Total CPU time to PAR completion: 9 mins 20 secs Peak Memory Usage:  352 MBPlacer: Placement generated during map.Routing: Completed - No errors found.Timing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 3Writing design to file routed.ncdPAR done!