Release 9.2.03i Map J.39Xilinx Mapping Report File for Design 'xilinx_pci_exp_4_lane_ep'Design Information------------------Command Line   : map -timing -ol high -xe c -pr b -o mapped.ncdendpoint_blk_plus_v1_5_top.ngd mapped.pcf Target Device  : xc5vlx50tTarget Package : ff1136Target Speed   : -1Mapper Version : virtex5 -- $Revision: 1.36 $Mapped Date    : Sun Dec  2 17:10:06 2007Design Summary--------------Number of errors:      0Number of warnings:    7Slice Logic Utilization:  Number of Slice Registers:                 2,888 out of  28,800   10%    Number used as Flip Flops:               2,884    Number used as Latches:                      4  Number of Slice LUTs:                      2,794 out of  28,800    9%    Number used as logic:                    2,574 out of  28,800    8%      Number using O6 output only:           2,318      Number using O5 output only:             137      Number using O5 and O6:                  119    Number used as Memory:                     204 out of   7,680    2%      Number used as Dual Port RAM:            136        Number using O6 output only:             8        Number using O5 output only:            64        Number using O5 and O6:                 64      Number used as Shift Register:            68        Number using O6 output only:            68    Number used as exclusive route-thru:        16  Number of route-thrus:                       164 out of  57,600    1%    Number using O6 output only:               150    Number using O5 output only:                11    Number using O5 and O6:                      3Slice Logic Distribution:  Number of occupied Slices:                 1,465 out of   7,200   20%  Number of LUT Flip Flop pairs used:        3,889    Number with an unused Flip Flop:         1,001 out of   3,889   25%    Number with an unused LUT:               1,095 out of   3,889   28%    Number of fully used LUT-FF pairs:       1,793 out of   3,889   46%    Number of unique control sets:             207  A LUT Flip Flop pair for this architecture represents one LUT paired with  one Flip Flop within a slice.  A control set is a unique combination of  clock, reset, set, and enable signals for a registered element.  The Slice Logic Distribution report is not meaningful if the design is  over-mapped for a non-slice resource or if Placement fails.IO Utilization:  Number of bonded IOBs:                         1 out of     480    1%Specific Feature Utilization:  Number of BlockRAM/FIFO:                       6 out of      60   10%    Number using BlockRAM only:                  6    Total primitives used:      Number of 36k BlockRAM used:               6    Total Memory used (KB):                    216 out of   2,160   10%  Number of BUFG/BUFGCTRLs:                      3 out of      32    9%    Number used as BUFGs:                        3  Number of BUFDSs:                              1 out of       6   16%  Number of DSP48Es:                             1 out of      48    2%  Number of GTP_DUALs:                           2 out of       6   33%  Number of PCIEs:                               1 out of       1  100%  Number of PLL_ADVs:                            1 out of       6   16%Total equivalent gate count for design:  863,171Additional JTAG gate count for IOBs:  912Peak Memory Usage:  434 MBTotal REAL time to MAP completion:  19 mins 7 secs Total CPU time to MAP completion:   19 mins 5 secs Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Control Set InformationSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:Map:165 - The command line option -timing is not supported for this   architecture, and will be ignored.WARNING:LIT:243 - Logical network cfg_to_turnoff_n_c has no load.WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 313   more times for the following (max. 5 shown):   trn_rd_c<63>,   trn_rd_c<55>,   trn_rd_c<51>,   trn_rd_c<50>,   trn_rd_c<49>   To see the details of these warning messages, please use the -detail switch.WARNING:PhysDesignRules:372 - Gated clock. Clock net   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0> is sourced by   a combinatorial pin. This is not good design practice. Use the CE pin to   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<2> is sourced by   a combinatorial pin. This is not good design practice. Use the CE pin to   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<3> is sourced by   a combinatorial pin. This is not good design practice. Use the CE pin to   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net   ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<1> is sourced by   a combinatorial pin. This is not good design practice. Use the CE pin to   control the loading of data into the flip-flop.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew   rate limited output drivers. The delay on speed critical single ended outputs   can be dramatically reduced by designating them as fast outputs in the   schematic.INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:   0.000 to 85.000 Celsius)INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to   1.050 Volts)INFO:Pack:1650 - Map created a placed design.Section 4 - Removed Logic Summary--------------------------------- 385 block(s) removed 186 block(s) optimized away 565 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic report below shows the logic removed from your design due tosourceless or loadless signals, and VCC or ground connections.  If the removalof a signal or symbol results in the subsequent removal of an additional signalor symbol, the message explaining that second removal will be indented.  Thisindentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, lookabove the place where that logic is listed in the trimming report, then locatethe lines that are least indented (begin at the leftmost edge).Loadless block "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg1"(CKBUF) removed. The signal "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_clk<0>" isloadless and has been removed.Loadless block "ep/BU2/U0/pcie_ep0/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg"(CKBUF) removed. The signal "ep/BU2/U0/pcie_ep0/pcie_blk/clocking_i/clkout2" is loadless and hasbeen removed.The signal "ep/trn_rfc_ph_av<7>" is sourceless and has been removed.The signal "ep/trn_rfc_ph_av<6>" is sourceless and has been removed.The signal "ep/trn_rfc_ph_av<5>" is sourceless and has been removed.The signal "ep/trn_rfc_ph_av<4>" is sourceless and has been removed.The signal "ep/trn_rfc_ph_av<3>" is sourceless and has been removed.The signal "ep/trn_rfc_ph_av<2>" is sourceless and has been removed.The signal "ep/trn_rfc_ph_av<1>" is sourceless and has been removed.The signal "ep/trn_rfc_ph_av<0>" is sourceless and has been removed.The signal "ep/trn_rbar_hit_n<6>" is sourceless and has been removed.The signal "ep/trn_rbar_hit_n<5>" is sourceless and has been removed.The signal "ep/trn_rbar_hit_n<4>" is sourceless and has been removed.The signal "ep/trn_rbar_hit_n<3>" is sourceless and has been removed.The signal "ep/trn_rbar_hit_n<2>" is sourceless and has been removed.The signal "ep/trn_rbar_hit_n<1>" is sourceless and has been removed.The signal "ep/trn_rbar_hit_n<0>" is sourceless and has been removed.The signal "ep/cfg_lcommand<15>" is sourceless and has been removed.The signal "ep/cfg_lcommand<14>" is sourceless and has been removed.The signal "ep/cfg_lcommand<13>" is sourceless and has been removed.The signal "ep/cfg_lcommand<12>" is sourceless and has been removed.The signal "ep/cfg_lcommand<11>" is sourceless and has been removed.The signal "ep/cfg_lcommand<10>" is sourceless and has been removed.The signal "ep/cfg_lcommand<9>" is sourceless and has been removed.The signal "ep/cfg_lcommand<8>" is sourceless and has been removed.The signal "ep/cfg_lcommand<7>" is sourceless and has been removed.The signal "ep/cfg_lcommand<6>" is sourceless and has been removed.The signal "ep/cfg_lcommand<5>" is sourceless and has been removed.The signal "ep/cfg_lcommand<4>" is sourceless and has been removed.The signal "ep/cfg_lcommand<3>" is sourceless and has been removed.The signal "ep/cfg_lcommand<2>" is sourceless and has been removed.The signal "ep/cfg_lcommand<1>" is sourceless and has been removed.The signal "ep/cfg_lcommand<0>" is sourceless and has been removed.The signal "ep/cfg_dstatus<15>" is sourceless and has been removed.The signal "ep/cfg_dstatus<14>" is sourceless and has been removed.The signal "ep/cfg_dstatus<13>" is sourceless and has been removed.The signal "ep/cfg_dstatus<12>" is sourceless and has been removed.The signal "ep/cfg_dstatus<11>" is sourceless and has been removed.The signal "ep/cfg_dstatus<10>" is sourceless and has been removed.The signal "ep/cfg_dstatus<9>" is sourceless and has been removed.The signal "ep/cfg_dstatus<8>" is sourceless and has been removed.The signal "ep/cfg_dstatus<7>" is sourceless and has been removed.The signal "ep/cfg_dstatus<6>" is sourceless and has been removed.The signal "ep/cfg_dstatus<5>" is sourceless and has been removed.The signal "ep/cfg_dstatus<4>" is sourceless and has been removed.The signal "ep/cfg_dstatus<3>" is sourceless and has been removed.The signal "ep/cfg_dstatus<2>" is sourceless and has been removed.The signal "ep/cfg_dstatus<1>" is sourceless and has been removed.The signal "ep/cfg_dstatus<0>" is sourceless and has been removed.The signal "ep/cfg_status<15>" is sourceless and has been removed.The signal "ep/cfg_status<14>" is sourceless and has been removed.The signal "ep/cfg_status<13>" is sourceless and has been removed.The signal "ep/cfg_status<12>" is sourceless and has been removed.The signal "ep/cfg_status<11>" is sourceless and has been removed.The signal "ep/cfg_status<10>" is sourceless and has been removed.The signal "ep/cfg_status<9>" is sourceless and has been removed.The signal "ep/cfg_status<8>" is sourceless and has been removed.The signal "ep/cfg_status<7>" is sourceless and has been removed.The signal "ep/cfg_status<6>" is sourceless and has been removed.The signal "ep/cfg_status<5>" is sourceless and has been removed.The signal "ep/cfg_status<4>" is sourceless and has been removed.The signal "ep/cfg_status<3>" is sourceless and has been removed.The signal "ep/cfg_status<2>" is sourceless and has been removed.The signal "ep/cfg_status<1>" is sourceless and has been removed.The signal "ep/cfg_status<0>" is sourceless and has been removed.The signal "ep/cfg_command<15>" is sourceless and has been removed.The signal "ep/cfg_command<14>" is sourceless and has been removed.The signal "ep/cfg_command<13>" is sourceless and has been removed.The signal "ep/cfg_command<12>" is sourceless and has been removed.The signal "ep/cfg_command<11>" is sourceless and has been removed.The signal "ep/cfg_command<9>" is sourceless and has been removed.The signal "ep/cfg_command<7>" is sourceless and has been removed.The signal "ep/cfg_command<5>" is sourceless and has been removed.The signal "ep/cfg_command<4>" is sourceless and has been removed.The signal "ep/cfg_command<3>" is sourceless and has been removed.The signal "ep/cfg_command<0>" is sourceless and has been removed.The signal "ep/cfg_do<31>" is sourceless and has been removed.The signal "ep/cfg_do<30>" is sourceless and has been removed.The signal "ep/cfg_do<29>" is sourceless and has been removed.The signal "ep/cfg_do<28>" is sourceless and has been removed.The signal "ep/cfg_do<27>" is sourceless and has been removed.The signal "ep/cfg_do<26>" is sourceless and has been removed.The signal "ep/cfg_do<25>" is sourceless and has been removed.The signal "ep/cfg_do<24>" is sourceless and has been removed.The signal "ep/cfg_do<23>" is sourceless and has been removed.The signal "ep/cfg_do<22>" is sourceless and has been removed.The signal "ep/cfg_do<21>" is sourceless and has been removed.The signal "ep/cfg_do<20>" is sourceless and has been removed.The signal "ep/cfg_do<19>" is sourceless and has been removed.The signal "ep/cfg_do<18>" is sourceless and has been removed.The signal "ep/cfg_do<17>" is sourceless and has been removed.The signal "ep/cfg_do<16>" is sourceless and has been removed.The signal "ep/cfg_do<15>" is sourceless and has been removed.The signal "ep/cfg_do<14>" is sourceless and has been removed.The signal "ep/cfg_do<13>" is sourceless and has been removed.The signal "ep/cfg_do<12>" is sourceless and has been removed.The signal "ep/cfg_do<11>" is sourceless and has been removed.The signal "ep/cfg_do<10>" is sourceless and has been removed.The signal "ep/cfg_do<9>" is sourceless and has been removed.The signal "ep/cfg_do<8>" is sourceless and has been removed.The signal "ep/cfg_do<7>" is sourceless and has been removed.The signal "ep/cfg_do<6>" is sourceless and has been removed.The signal "ep/cfg_do<5>" is sourceless and has been removed.The signal "ep/cfg_do<4>" is sourceless and has been removed.The signal "ep/cfg_do<3>" is sourceless and has been removed.The signal "ep/cfg_do<2>" is sourceless and has been removed.The signal "ep/cfg_do<1>" is sourceless and has been removed.The signal "ep/cfg_do<0>" is sourceless and has been removed.The signal "ep/trn_rerrfwd_n" is sourceless and has been removed.The signal "ep/cfg_dcommand<15>" is sourceless and has been removed.The signal "ep/cfg_dcommand<11>" is sourceless and has been removed.The signal "ep/cfg_dcommand<10>" is sourceless and has been removed.The signal "ep/cfg_dcommand<4>" is sourceless and has been removed.The signal "ep/cfg_dcommand<1>" is sourceless and has been removed.The signal "ep/cfg_rd_wr_done_n" is sourceless and has been removed. Sourceless block"ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/lock_useraccess_or00001" (ROM) removed.  The signal"ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/lock_useraccess_not0002_inv" is sourceless and has been removed. Sourceless block"ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/cfg_rd_en_n_d_or000011_INV_0" (BUF) removed.  The signal "ep/BU2/U0/pcie_ep0/pcie_blk_if/N3345" is sourceless and has been