Release 9.2.03i Map J.39Xilinx Map Application Log File for Design 'xilinx_pci_exp_4_lane_ep'Design Information------------------Command Line   : map -timing -ol high -xe c -pr b -o mapped.ncdendpoint_blk_plus_v1_5_top.ngd mapped.pcf Target Device  : xc5vlx50tTarget Package : ff1136Target Speed   : -1Mapper Version : virtex5 -- $Revision: 1.36 $Mapped Date    : Sun Dec  2 17:10:06 2007Mapping design into LUTs...Writing file mapped.ngm...Running directed packing...Running delay-based LUT packing...Running timing-driven packing...Phase 1.1Phase 1.1 (Checksum:9b00b8) REAL time: 1 mins 44 secs Phase 2.7Phase 2.7 (Checksum:1312cfe) REAL time: 1 mins 44 secs Phase 3.31Phase 3.31 (Checksum:1c9c37d) REAL time: 1 mins 44 secs Phase 4.33Phase 4.33 (Checksum:26259fc) REAL time: 4 mins 23 secs Phase 5.32Phase 5.32 (Checksum:2faf07b) REAL time: 4 mins 25 secs Phase 6.2.Phase 6.2 (Checksum:39386fa) REAL time: 4 mins 42 secs Phase 7.30Phase 7.30 (Checksum:42c1d79) REAL time: 4 mins 42 secs Phase 8.3Phase 8.3 (Checksum:4c4b3f8) REAL time: 4 mins 45 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 4 mins 46 secs Phase 10.8..................................................................................................................................................................................................Phase 10.8 (Checksum:14a6c5c) REAL time: 7 mins 20 secs Phase 11.29Phase 11.29 (Checksum:68e7775) REAL time: 7 mins 20 secs Phase 12.5Phase 12.5 (Checksum:7270df4) REAL time: 7 mins 21 secs Phase 13.18Phase 13.18 (Checksum:7bfa473) REAL time: 15 mins 34 secs Phase 14.5Phase 14.5 (Checksum:8583af2) REAL time: 15 mins 34 secs Phase 16.34Phase 16.34 (Checksum:98967f0) REAL time: 15 mins 35 secs REAL time consumed by placer: 15 mins 36 secs CPU  time consumed by placer: 15 mins 34 secs Inspecting route info ...Route info done.Design Summary--------------Design Summary:Number of errors:      0Number of warnings:    7Slice Logic Utilization:  Number of Slice Registers:                 2,888 out of  28,800   10%    Number used as Flip Flops:               2,884    Number used as Latches:                      4  Number of Slice LUTs:                      2,794 out of  28,800    9%    Number used as logic:                    2,574 out of  28,800    8%      Number using O6 output only:           2,318      Number using O5 output only:             137      Number using O5 and O6:                  119    Number used as Memory:                     204 out of   7,680    2%      Number used as Dual Port RAM:            136        Number using O6 output only:             8        Number using O5 output only:            64        Number using O5 and O6:                 64      Number used as Shift Register:            68        Number using O6 output only:            68    Number used as exclusive route-thru:        16  Number of route-thrus:                       164 out of  57,600    1%    Number using O6 output only:               150    Number using O5 output only:                11    Number using O5 and O6:                      3Slice Logic Distribution:  Number of occupied Slices:                 1,465 out of   7,200   20%  Number of LUT Flip Flop pairs used:        3,889    Number with an unused Flip Flop:         1,001 out of   3,889   25%    Number with an unused LUT:               1,095 out of   3,889   28%    Number of fully used LUT-FF pairs:       1,793 out of   3,889   46%    Number of unique control sets:             207  A LUT Flip Flop pair for this architecture represents one LUT paired with  one Flip Flop within a slice.  A control set is a unique combination of  clock, reset, set, and enable signals for a registered element.  The Slice Logic Distribution report is not meaningful if the design is  over-mapped for a non-slice resource or if Placement fails.IO Utilization:  Number of bonded IOBs:                         1 out of     480    1%Specific Feature Utilization:  Number of BlockRAM/FIFO:                       6 out of      60   10%    Number using BlockRAM only:                  6    Total primitives used:      Number of 36k BlockRAM used:               6    Total Memory used (KB):                    216 out of   2,160   10%  Number of BUFG/BUFGCTRLs:                      3 out of      32    9%    Number used as BUFGs:                        3  Number of BUFDSs:                              1 out of       6   16%  Number of DSP48Es:                             1 out of      48    2%  Number of GTP_DUALs:                           2 out of       6   33%  Number of PCIEs:                               1 out of       1  100%  Number of PLL_ADVs:                            1 out of       6   16%Total equivalent gate count for design:  863,171Additional JTAG gate count for IOBs:  912Peak Memory Usage:  434 MBTotal REAL time to MAP completion:  19 mins 7 secs Total CPU time to MAP completion:   19 mins 5 secs Mapping completed.See MAP report file "mapped.mrp" for details.