Release 9.2.03i - netgen J.39Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.Command Line: netgen -sim -ofmt verilog -ne -w -tm xilinx_pci_exp_4_lane_ep-sdf_path ../../implement/results routed.ncd  Read and Annotate design 'routed.ncd' ...Loading device for application Rf_Device from file '5vlx50t.nph' in environment/program/ise92.   "xilinx_pci_exp_4_lane_ep" is an NCD, version 3.1, device xc5vlx50t, packageff1136, speed -1The number of routable networks is 4865Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing Verilog SDF file '../../implement/results/routed.sdf' ...Writing Verilog netlist file 'routed.v' ...INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM   simulation primitives and has to be used with SIMPRIM simulation library for   correct compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 259020 kilobytes