//-f ./unisims.f
//-f ./simprims.f

../sim_define.v
../board_common.v


// PCI-Express 1 Lane Endpoint Reference Design
//----------------------------------------------

../../example_design/xilinx_pci_exp_1_lane_ep_product.v
../xilinx_pci_exp_defines.v

../../example_design/BMD_64.v
../../example_design/BMD.v
../../example_design/BMD_64_RX_ENGINE.v
../../example_design/BMD_64_TX_ENGINE.v
../../example_design/BMD_EP_MEM_ACCESS.v
../../example_design/BMD_EP_MEM.v
../../example_design/BMD_EP.v
../../example_design/BMD_INTR_CTRL.v
../../example_design/BMD_TO_CTRL.v../../example_design/xilinx_pci_exp_1_lane_ep.v
../../example_design/pci_exp_64b_app.v
../../../endpoint_blk_plus_v1_5.v


../board.v


//Xilinx PCI Express Root Complex Model
//--------------------------------------------
../dsport/xilinx_pci_exp_downstream_port.v
../dsport/xilinx_pci_exp_dsport.v
../dsport/dsport_cfg.v
../dsport/pci_exp_usrapp_rx.v
../dsport/pci_exp_usrapp_tx.v
../dsport/pci_exp_usrapp_com.v
../dsport/pci_exp_usrapp_cfg.v
../dsport/pci_exp_1_lane_64b_dsport.v

../sys_clk_gen.v
../sys_clk_gen_ds.v