library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.std_logic_arith.all;

entity srl16 is
port (	Q     : out std_logic;
	   Clk    : in  std_logic;
	    A     : in  std_logic_VECTOR(3 DOWNTO 0);
	    D     : in  std_logic);
end srl16;

architecture RTL of SRL16 is
begin


process (Clk)
variable shift: std_logic_vector(15 downto 0);
 
begin
   if rising_edge(clk) then           
    case  A is
	   when "0000"=>   q<=shift(0);
       when "0001"=>   q<=shift(1);
	   when "0010"=>   q<=shift(2);
       when "0011"=>   q<=shift(3);
       when "0100"=>   q<=shift(4);
	   when "0101"=>   q<=shift(5);
       when "0110"=>   q<=shift(6);
	   when "0111"=>   q<=shift(7);
       when "1000"=>   q<=shift(8);
       when "1001"=>   q<=shift(9);
	   when "1010"=>   q<=shift(10);
       when "1011"=>   q<=shift(11);
	   when "1100"=>   q<=shift(12);
       when "1101"=>   q<=shift(13);
       when "1110"=>   q<=shift(14);
	   when "1111"=>   q<=shift(15);
       when  others=>  q<=d;
	end case;
    shift:=shift(14 downto 0) & d ;
end if;
end process;

end RTL;