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?? the synthetic pic.mht

?? VERILOG VERSION PIC16C57 是一個用于FPGA模擬PIC16C57的IP核
?? MHT
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Subject: The Synthetic PIC
Date: Fri, 20 Feb 2009 21:26:15 +0800
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  <o:Revision>3</o:Revision>
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  <o:Created>2001-05-05T12:35:00Z</o:Created>
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  <o:Company>Scientific Atlanta, Inc.</o:Company>
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<P class=3DMsoNormal><SPAN style=3D"DISPLAY: none; mso-hide: =
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<P>These files are a VHDL synthesizable model for the MICROCHIP PIC =
16C5X=20
microcontroller. Look at SYNTHPIC.TXT for brief description (which is =
included=20
in the ZIP file). This VHDL implementation is currently a ViewLogic=20
implementation, but is very synthesizable and should be very easy to =
port.=20
CURRENT VERSION is V1.1 </P>
<P>Paolo Navaretti has graciously updated my old VHDL code to IEEE. Many =
people=20
have asked for this, so thanks Paolo. It is a UNIX Tar and zipped. Sorry =
it took=20
so long...=20
<P><BR><A=20
href=3D"http://www.mindspring.com/~tcoonan/picieee.tar.gz">picieee.tar.gz=
</A>.....Updateed=20
IEEE version of Synthetic PIC (~10KB) <BR>
<P><BR><A=20
href=3D"http://www.mindspring.com/~tcoonan/synthpic.zip">SYNTHPIC.ZIP</A>=
.....ZIP=20
file for Synthetic PIC (not IEEE..) (~48KB) <BR><A=20
href=3D"http://www.mindspring.com/~tcoonan/synthpic.txt">SYNTHPIC.TXT</A>=
.....Brief=20
technical text description </P>
<P>I have not been using VHDL for a while and primarily use Verilog =
where I=20
work.<SPAN style=3D"mso-spacerun: yes">&nbsp; </SPAN>See my latest <A=20
href=3D"http://www.mindspring.com/~tcoonan/newpic.html">Verilog =
version</A>. This=20
Verilog version is the newest version and has several enhancements.<SPAN =

style=3D"mso-spacerun: yes">&nbsp; </SPAN>It is also the version that I =
have made=20
available at <A =
href=3D"http://www.free-ip.com/">http://www.free-ip.com/</A> where=20
other Open Source hardware cores are available.<SPAN=20
style=3D"mso-spacerun: yes">&nbsp; </SPAN>Also, at <A=20
href=3D"http://www.free-ip.com/">http://www.free-ip.com/</A>, are is =
another VHDL=20
version of my core someone else has updated.<SPAN=20
style=3D"mso-spacerun: yes">&nbsp; </SPAN>So, look around for the =
version that=20
makes the most sense for you.</P>
<P>This version and the Verilog version have been implemented in a =
myriad of=20
FPGAs and even several ASICs.<SPAN style=3D"mso-spacerun: yes">&nbsp; =
</SPAN>While=20
this is completely =E2=80=9CAs Is=E2=80=9D, I hope you can use it for =
learning purposes or in=20
your real-world applications.</P>
<P>Thanks for everyone's interest! I hope the Synthetic PIC proves =
useful for=20
the Core and/or Reconfigurable Computing projects, or as an example of a =

synthesizable VHDL processor. </P>
<P>Some PIC links: <BR><A href=3D"http://www.elabinc.com/">E-Labs - a =
nice PIC=20
page</A> <BR><A href=3D"http://www.microchip.com/">And, of course, the =
MICROCHIP=20
page.</A> </P>
<P><A href=3D"http://www.mindspring.com/~tcoonan/index.html">Back to Tom =
Coonan's=20
Home Page (email link is there)</A> <BR=20
style=3D"mso-special-character: line-break" clear=3Dright></P>
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