?? adcinc_1.lis
字號:
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000 ;; FILENAME: ADCINC_1.asm
0000 ;; Version: 1.1, Updated on 2005/09/29 at 13:17:03
0000 ;; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
0000 ;;
0000 ;; DESCRIPTION: Assembler source for the ADCINC A/D Converter
0000 ;; User Module with 2nd-order modulator.
0000 ;;
0000 ;; NOTE: User Module APIs conform to the fastcall16 convention for marshalling
0000 ;; arguments and observe the associated "Registers are volatile" policy.
0000 ;; This means it is the caller's responsibility to preserve any values
0000 ;; in the X and A registers that are still needed after the API
0000 ;; function returns. Even though these registers may be preserved now,
0000 ;; there is no guarantee they will be preserved in future releases.
0000 ;;-----------------------------------------------------------------------------
0000 ;; Copyright (c) Cypress MicroSystems 2000-2004. All Rights Reserved.
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000
0010 FLAG_XIO_MASK: equ 10h
0008 FLAG_SUPER: equ 08h
0004 FLAG_CARRY: equ 04h
0002 FLAG_ZERO: equ 02h
0001 FLAG_GLOBAL_IE: equ 01h
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
0013 PRT4DM2: equ 13h ; Port 4 Drive Mode 2 (RW)
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (RW)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (RW)
0017 PRT5DM2: equ 17h ; Port 5 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03DR0: equ 2Ch ; data register 0 (#)
002D DCB03DR1: equ 2Dh ; data register 1 (W)
002E DCB03DR2: equ 2Eh ; data register 2 (RW)
002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 10, Basic Type B
0030 DBB10DR0: equ 30h ; data register 0 (#)
0031 DBB10DR1: equ 31h ; data register 1 (W)
0032 DBB10DR2: equ 32h ; data register 2 (RW)
0033 DBB10CR0: equ 33h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 11, Basic Type B
0034 DBB11DR0: equ 34h ; data register 0 (#)
0035 DBB11DR1: equ 35h ; data register 1 (W)
0036 DBB11DR2: equ 36h ; data register 2 (RW)
0037 DBB11CR0: equ 37h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 12, Communications Type B
0038 DCB12DR0: equ 38h ; data register 0 (#)
0039 DCB12DR1: equ 39h ; data register 1 (W)
003A DCB12DR2: equ 3Ah ; data register 2 (RW)
003B DCB12CR0: equ 3Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 13, Communications Type B
003C DCB13DR0: equ 3Ch ; data register 0 (#)
003D DCB13DR1: equ 3Dh ; data register 1 (W)
003E DCB13DR2: equ 3Eh ; data register 2 (RW)
003F DCB13CR0: equ 3Fh ; control & status register 0 (#)
0000
0000 ;-------------------------------------
0000 ; Analog Resource Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
00C0 AMX_IN_ACI3: equ C0h ; MASK: column 3 input mux
0030 AMX_IN_ACI2: equ 30h ; MASK: column 2 input mux
000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
0000
0063 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
0040 ARF_CR_HBE: equ 40h ; MASK: Bias level control
0038 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
0007 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
0004 ARF_CR_APWR: equ 04h ; MASK: use deprecated; see datasheet
0003 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
0000
0064 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
0080 CMP_CR0_COMP3: equ 80h ; MASK: Column 3 comparator state (R)
0040 CMP_CR0_COMP2: equ 40h ; MASK: Column 2 comparator state (R)
0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
0008 CMP_CR0_AINT3: equ 08h ; MASK: Column 3 interrupt source (RW)
0004 CMP_CR0_AINT2: equ 04h ; MASK: Column 2 interrupt source (RW)
0002 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
0001 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
0000
0065 ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
0070 ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
0008 ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
0006 ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
0001 ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
0000
0066 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
0080 CMP_CR1_ASYNCH3: equ 80h ; MASK: Column 3 comparator bus synch
0040 CMP_CR1_ASYNCH2: equ 40h ; MASK: Column 2 comparator bus synch
0020 CMP_CR1_ASYNCH1: equ 20h ; MASK: Column 1 comparator bus synch
0010 CMP_CR1_ASYNCH0: equ 10h ; MASK: Column 0 comparator bus synch
0000
0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;---------------------------------------------------
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 0
0070 ACB00CR3: equ 70h ; Control register 3 (RW)
0071 ACB00CR0: equ 71h ; Control register 0 (RW)
0072 ACB00CR1: equ 72h ; Control register 1 (RW)
0073 ACB00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 1
0074 ACB01CR3: equ 74h ; Control register 3 (RW)
0075 ACB01CR0: equ 75h ; Control register 0 (RW)
0076 ACB01CR1: equ 76h ; Control register 1 (RW)
0077 ACB01CR2: equ 77h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 2
0078 ACB02CR3: equ 78h ; Control register 3 (RW)
0079 ACB02CR0: equ 79h ; Control register 0 (RW)
007A ACB02CR1: equ 7Ah ; Control register 1 (RW)
007B ACB02CR2: equ 7Bh ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 3
007C ACB03CR3: equ 7Ch ; Control register 3 (RW)
007D ACB03CR0: equ 7Dh ; Control register 0 (RW)
007E ACB03CR1: equ 7Eh ; Control register 1 (RW)
007F ACB03CR2: equ 7Fh ; Control register 2 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 1 Col 0
0080 ASC10CR0: equ 80h ; Control register 0 (RW)
0081 ASC10CR1: equ 81h ; Control register 1 (RW)
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