?? _primary.vhd
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library verilog;use verilog.vl_types.all;entity mul is port( clk : in vl_logic; nrst : in vl_logic; a : in vl_logic_vector(7 downto 0); b : in vl_logic_vector(7 downto 0); mul_en : in vl_logic; oen : out vl_logic; product : out vl_logic_vector(15 downto 0) );end mul;
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