?? _primary.vhd
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library verilog;use verilog.vl_types.all;entity stackc is port( clk : in vl_logic; nrst : in vl_logic; push : in vl_logic; pop : in vl_logic; wptr : out vl_logic_vector(3 downto 0); rptr : out vl_logic_vector(3 downto 0); pre_empty : out vl_logic; empty : out vl_logic; pre_full : out vl_logic; full : out vl_logic; overflow : out vl_logic );end stackc;
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