?? controllogic.vhd
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signal IDR_TEQ : std_logic := '0';
signal IDR_ADD : std_logic := '0';
signal IDR_ADC : std_logic := '0';
signal IDR_SUB : std_logic := '0';
signal IDR_SBC : std_logic := '0';
signal IDR_RSB : std_logic := '0';
signal IDR_RSC : std_logic := '0';
signal IDR_CMP : std_logic := '0';
signal IDR_CMN : std_logic := '0';
signal IDR_MOV : std_logic := '0';
signal IDR_MVN : std_logic := '0';
-- Multiplications
signal IDR_MUL : std_logic := '0';
signal IDR_MLA : std_logic := '0';
signal IDR_UMULL : std_logic := '0';
signal IDR_UMLAL : std_logic := '0';
signal IDR_SMULL : std_logic := '0';
signal IDR_SMLAL : std_logic := '0';
--SPSR Move
signal IDR_MSR_R : std_logic := '0'; -- Register operand
signal IDR_MSR_I : std_logic := '0'; -- Immediate operand
signal IDR_MRS : std_logic := '0';
-- Branch
signal IDR_B : std_logic := '0';
signal IDR_BL : std_logic := '0';
signal IDR_BX : std_logic := '0';
-- Load
signal IDR_LDR : std_logic := '0';
signal IDR_LDRT : std_logic := '0';
signal IDR_LDRB : std_logic := '0';
signal IDR_LDRBT : std_logic := '0';
signal IDR_LDRSB : std_logic := '0';
signal IDR_LDRH : std_logic := '0';
signal IDR_LDRSH : std_logic := '0';
signal IDR_LDM : std_logic := '0'; -- ?? Variants
-- Store
signal IDR_STR : std_logic := '0';
signal IDR_STRT : std_logic := '0';
signal IDR_STRB : std_logic := '0';
signal IDR_STRBT : std_logic := '0';
signal IDR_STRH : std_logic := '0';
signal IDR_STM : std_logic := '0'; -- ?? Variants
-- Swap
signal IDR_SWP : std_logic := '0';
signal IDR_SWPB : std_logic := '0';
signal IDR_SWI : std_logic := '0';
-- Coprocessor communication instructions
signal IDR_MRC : std_logic := '0';
signal IDR_MCR : std_logic := '0';
signal IDR_LDC : std_logic := '0';
signal IDR_CDP : std_logic := '0';
signal IDR_STC : std_logic := '0';
-- Undefined instruction
signal IDR_Undef : std_logic := '0';
-- Thumb branch with link support
signal IDR_ThBLFP : std_logic := '0'; -- Can appear only in Thumb mode
signal IDR_ThBLSP : std_logic := '0'; -- Can appear only in Thumb mode
-- End of registeres instruction decoder outputs
-- Instructions groops
-- Arithmetic instructions extension space
signal IDC_ArInstExtSp : std_logic := '0'; -- Bit[25](I)='0' and Bit[7](I)='1' and Bit[4](I)='1'
signal IDC_DPIRegSh : std_logic := '0'; -- Data processing register shift
signal IDC_DPIImmSh : std_logic := '0'; -- Data processing immediate shift
signal IDC_DPIImmRot : std_logic := '0'; -- Data processing immediate(rotate)
signal IDC_LSRegOffset : std_logic := '0'; -- Load/store(word/byte) register offset
signal IDC_LSImmOffset : std_logic := '0'; -- Load/store(word/byte) immediate offset
signal IDC_LSHWImmOffset : std_logic := '0'; -- Load/store(halfword) immediate offset
signal IDC_LSHWRegOffset : std_logic := '0'; -- Load/store(halfword) register offset
signal IDC_LHWBSImmOffset : std_logic := '0'; -- Load signed (halfword/byte) immediate offset
signal IDC_LHWBSRegOffset : std_logic := '0'; -- Load signed (halfword/byte) register offset
signal IDC_LdStInst : std_logic := '0'; -- Load/strore single or multiple
signal IDC_Branch : std_logic := '0';
signal IDC_Compare : std_logic := '0';
signal IDC_DPIArith : std_logic := '0'; -- Data processing instructions writing V flag
-- Registered signals
signal IDR_DPIRegSh : std_logic := '0';
signal IDR_DPIImmSh : std_logic := '0';
signal IDR_DPIImmRot : std_logic := '0';
signal IDR_LSRegOffset : std_logic := '0';
signal IDR_LSImmOffset : std_logic := '0';
signal IDR_LSHWImmOffset : std_logic := '0';
signal IDR_LSHWRegOffset : std_logic := '0';
signal IDR_LHWBSImmOffset : std_logic := '0';
signal IDR_LHWBSRegOffset : std_logic := '0';
signal IDR_LdStInst : std_logic := '0'; -- Load/strore single or multiple
signal IDR_Branch : std_logic := '0';
signal IDR_Compare : std_logic := '0';
signal IDR_DPIArith : std_logic := '0';
-- Single cycle data processing instruction
signal IDR_SingleCycleDPI : std_logic := '0';
-- Instruction state machines (cycle count ??)
-- Data processing instruction with shift by Rs (2 cycles - additional cycle for simple DPI)
signal DPIRegSh_St : std_logic := '0';
-- Data processing/load instruction writes to PC
signal nWrPCSM_St0 : std_logic := '0';
signal WrPCSM_St1 : std_logic := '0';
signal WrPCSM_St2 : std_logic := '0';
-- Load register (3 cycle)
signal nLDR_St0 : std_logic := '0';
signal LDR_St1 : std_logic := '0';
signal LDR_St2 : std_logic := '0';
-- Load multiple registers (up to ? cycle)
signal nLDM_St0 : std_logic := '0';
signal LDM_St1 : std_logic := '0';
signal LDM_St2 : std_logic := '0';
-- Store register (2 cycle)
signal STR_St : std_logic := '0';
-- Load multiple registers (up to ? cycle)
signal STM_St : std_logic := '0';
-- Access to User Mode Registers during LDM/STM (special form - ^)
signal UMRAccess_St : std_logic := '0';
signal LSMUMR : std_logic := '0'; -- Load/store multiple User Mode Registers
signal UpDBaseRSng : std_logic := '0'; -- Update base register for single load/store
-- TBD
-- Multiplications
-- MUL
signal MUL_St : std_logic := '0';
-- MLA
signal nMLA_St0 : std_logic := '0';
signal MLA_St1 : std_logic := '0';
signal MLA_St2 : std_logic := '0';
-- SMULL/UMULL
signal nMULL_St0 : std_logic := '0';
signal MULL_St1 : std_logic := '0';
signal MULL_St2 : std_logic := '0';
-- SMLAL/UMLAL
signal nMLAL_St0 : std_logic := '0';
signal MLAL_St1 : std_logic := '0';
signal MLAL_St2 : std_logic := '0';
signal MLAL_St3 : std_logic := '0';
signal BaseRegUdate_St : std_logic := '0';
signal BaseRegWasUdated_St : std_logic := '0';
signal LSMCycleCnt : std_logic_vector(4 downto 0) := (others => '0');
type RegNumCntType is array (0 to 15) of std_logic_vector(4 downto 0);
signal RegNumCnt : RegNumCntType := (others => "00000");
signal LSMStop : std_logic := '0';
signal LSMStopDel : std_logic := '0';
-- Next register address calculation
signal CurrentRgAdr : std_logic_vector (3 downto 0) := (others => '0');
signal FirstRgAdr : std_logic_vector (3 downto 0) := (others => '0');
type NextRgAdrType is array (0 to 15) of std_logic_vector(3 downto 0);
signal NextRgAdr : NextRgAdrType := (others => "0000");
signal RgAdr : NextRgAdrType := (others => "0000");
-- Swap (4 cycle)
signal nSWP_St0 : std_logic := '0';
signal SWP_St1 : std_logic := '0';
signal SWP_St2 : std_logic := '0';
signal SWP_St3 : std_logic := '0';
-- Branch (3 cycle)
signal nBranch_St0 : std_logic := '0';
signal Branch_St1 : std_logic := '0';
signal Branch_St2 : std_logic := '0';
signal BLink : std_logic := '0'; -- Link indicator for branch with link
-- Exception state machine
signal ExceptSMStart : std_logic := '0';
signal nExceptSM_St0 : std_logic := '0';
signal ExceptSM_St1 : std_logic := '0';
signal ExceptSM_St2 : std_logic := '0';
signal ExceptFC : std_logic := '0'; -- The first cycle of exception
-- Individual exception start signals
signal DAbtExcStart : std_logic := '0'; -- Data abort exception start
signal FIQExcStart : std_logic := '0'; -- FIQ exception start
signal IRQExcStart : std_logic := '0'; -- IRQ exception start
signal PAbtExcStart : std_logic := '0'; -- Prefetch abort exception start
signal SWI_UndefExcStart : std_logic := '0'; -- SWI or undefined instruction exception start
-- Latched interrupt request
signal FIQLatched : std_logic := '0';
signal IRQLatched : std_logic := '0';
-- Various data aborts
signal DAbtFlag : std_logic := '0';
signal LSAbtOccurred : std_logic := '0';
signal DAbtStored : std_logic := '0';
-- New CPSR mode
signal NewMode : std_logic_vector(4 downto 0) := (others => '0');
signal NewFFlag : std_logic := '0';
signal NewIFlag : std_logic := '0';
signal NewTFlag : std_logic := '0';
-- Pipeline stagnation
signal StagnatePipeline_Int : std_logic := '0';
-- StagnatePipeline signal delayed by one clock cycle
signal StagnatePipelineDel_Int : std_logic := '0';
-- First instruction fetch after reset
signal FirstInstFetch_Int : std_logic := '0';
-- Pipeline refilling
signal PipelineRefilling : std_logic := '0';
-- Conditional execution
signal ConditionIsTrue : std_logic := '0';
signal ExecuteInst : std_logic := '0';
alias CPSRNFlag : std_logic is CPSROut(31);
alias CPSRZFlag : std_logic is CPSROut(30);
alias CPSRCFlag : std_logic is CPSROut(29);
alias CPSRVFlag : std_logic is CPSROut(28);
alias CPSRIFlag : std_logic is CPSROut(7);
alias CPSRFFlag : std_logic is CPSROut(6);
alias CPSRTFlag : std_logic is CPSROut(5);
alias CPSRMode : std_logic_vector(4 downto 0) is CPSROut(4 downto 0);
-- CPSR write enable signals
--alias CPSRNFlWE : std_logic is CPSRWrEn(31);
--alias CPSRZFlWE : std_logic is CPSRWrEn(30);
--alias CPSRCFlWE : std_logic is CPSRWrEn(29);
--alias CPSRVFlWE : std_logic is CPSRWrEn(28);
--alias CPSRTFlWE : std_logic is CPSRWrEn(5);
signal CPSRNFlWE : std_logic := '0';
signal CPSRZFlWE : std_logic := '0';
signal CPSRCFlWE : std_logic := '0';
signal CPSRVFlWE : std_logic := '0';
signal CPSRIFlWE : std_logic := '0';
signal CPSRFFlWE : std_logic := '0';
signal CPSRTFlWE : std_logic := '0';
signal CPSRModeWE : std_logic := '0'; -- Permits write to CPSR[4:0]
-- Internal signals for the flags which can be generated in different ways
signal NewZFlag : std_logic := '0';
-- Register file control signals(internal copies of outputs)
signal WriteAdr_Int : std_logic_vector(WriteAdr'range);
signal WrEn_Int : std_logic := '0';
-- Additional control signals for ALU and A-Bus multiplexer (for exceptions)
signal PassA_Reg : std_logic := '0';
signal PassB_Reg : std_logic := '0';
signal RegFileAOutSel_Reg : std_logic := '0';
signal MultiplierAOutSel_Reg : std_logic := '0';
signal CPSROutSel_Reg : std_logic := '0';
signal SPSROutSel_Reg : std_logic := '0';
signal ClrBitZero_Reg : std_logic := '0';
signal ClrBitOne_Reg : std_logic := '0';
signal SetBitZero_Reg : std_logic := '0';
begin
-- *******************************************************************************************
-- Instruction decoder
-- *******************************************************************************************
-- Arithmetic instruction extension space
IDC_ArInstExtSp <= '1' when InstForDecode(25)='0' and InstForDecode(7)='1' and
InstForDecode(4)='1' else '0';
-- Data processing instructions
IDC_AND <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0000" and
IDC_ArInstExtSp='0' else '0';
IDC_EOR <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0001" and
IDC_ArInstExtSp='0' else '0';
IDC_ORR <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="1100" and
IDC_ArInstExtSp='0' else '0';
IDC_BIC <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="1110" and
IDC_ArInstExtSp='0' else '0';
IDC_ADD <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0100" and
IDC_ArInstExtSp='0' else '0';
IDC_ADC <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0101" and
IDC_ArInstExtSp='0' else '0';
IDC_SUB <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0010" and
IDC_ArInstExtSp='0' else '0';
IDC_SBC <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0110" and
IDC_ArInstExtSp='0' else '0';
IDC_RSB <= '1' when InstForDecode(27 downto 26)="00" and
InstForDecode(24 downto 21)="0011" and
IDC_ArInstExtSp='0' else '0';
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