//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_ddr2_top_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Wed Aug 16 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   System level module. This level contains just the memory controller.
//   This level will be intiantated when the user wants to remove the
//   synthesizable test bench, IDELAY control block and the clock
//   generation modules.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_ddr2_top_0 #
  (
   parameter BANK_WIDTH     = 3,      // # of memory bank addr bits
   parameter CKE_WIDTH      = 1,      // # of memory clock enable outputs
   parameter CLK_WIDTH      = 1,      // # of clock outputs
   parameter COL_WIDTH      = 10,     // # of memory column bits
   parameter CS_NUM         = 1,      // # of separate memory chip selects
   parameter CS_BITS        = 0,      // set to log2(CS_NUM) (rounded up)
   parameter CS_WIDTH       = 1,      // # of total memory chip selects
   parameter DM_WIDTH       = 9,      // # of data mask bits
   parameter DQ_WIDTH       = 72,     // # of data width
   parameter DQ_BITS        = 7,      // set to log2(DQS_WIDTH*DQ_PER_DQS)
   parameter DQ_PER_DQS     = 8,      // # of DQ data bits per strobe
   parameter DQS_WIDTH      = 9,      // # of DQS strobes
   parameter DQS_BITS       = 4,      // set to log2(DQS_WIDTH)
   parameter ODT_WIDTH      = 1,      // # of memory on-die term enables
   parameter ROW_WIDTH      = 14,     // # of memory row & # of addr bits
   parameter ADDITIVE_LAT   = 0,      // additive write latency
   parameter BURST_LEN      = 4,      // burst length (in double words)
   parameter BURST_TYPE     = 0,      // burst type (=0 seq; =1 interlved)
   parameter CAS_LAT        = 3,      // CAS latency
   parameter ECC_ENABLE     = 0,      // enable ECC (=1 enable)
   parameter ODT_TYPE       = 0,      // ODT (=0(none),=1(75),=2(150),=3(50))
   parameter MULTI_BANK_EN  = 1,      // enable bank management
   parameter REDUCE_DRV     = 0,      // reduced strength mem I/O (=1 yes)
   parameter REG_ENABLE     = 1,      // registered addr/ctrl (=1 yes)
   parameter TREFI_NS       = 7800,   // auto refresh interval (uS)
   parameter TRAS           = 40000,  // active->precharge delay
   parameter TRCD           = 15000,  // active->read/write delay
   parameter TRFC           = 127500, // ref->ref, ref->active delay
   parameter TRP            = 15000,  // precharge->command delay
   parameter TRTP           = 7500,   // read->precharge delay
   parameter TWR            = 15000,  // used to determine wr->prech
   parameter TWTR           = 10000,  // write->read delay
   parameter CLK_PERIOD     = 5000,   // Core/Mem clk period (in ps)
   parameter IDEL_HIGH_PERF = "TRUE", // IDELAY low jitter mode
   parameter SIM_ONLY       = 0       // = 1 to skip power up delay
   )
  (
   input                                    clk0,
   input                                    clk90,
   input                                    rst0,
   input                                    rst90,
   input [2:0]                              app_af_cmd,
   input [30:0]                             app_af_addr,
   input                                    app_af_wren,
   input                                    app_wdf_wren,
   input [(2*DQ_WIDTH)-1:0]                 app_wdf_data,
   input [((2*DQ_WIDTH)/8)-1:0]             app_wdf_mask_data,
   output                                   app_af_afull,
   output                                   app_wdf_afull,
   output                                   rd_data_valid,
   output [(2*DQ_WIDTH)-1:0]                rd_data_fifo_out,
   output                                   phy_init_done,
   output [CLK_WIDTH-1:0]                   ddr2_ck,
   output [CLK_WIDTH-1:0]                   ddr2_ck_n,
   output [ROW_WIDTH-1:0]                   ddr2_a,
   output [BANK_WIDTH-1:0]                  ddr2_ba,
   output                                   ddr2_ras_n,
   output                                   ddr2_cas_n,
   output                                   ddr2_we_n,
   output [CS_WIDTH-1:0]                    ddr2_cs_n,
   output [CKE_WIDTH-1:0]                   ddr2_cke,
   output [ODT_WIDTH-1:0]                   ddr2_odt,
   output [DM_WIDTH-1:0]                    ddr2_dm,
   inout [DQS_WIDTH-1:0]                    ddr2_dqs,
   inout [DQS_WIDTH-1:0]                    ddr2_dqs_n,
   inout [DQ_WIDTH-1:0]                     ddr2_dq
   );


  // memory initialization/control logic
  mem_interface_top_mem_if_top_0 #
    (
     .BANK_WIDTH     (BANK_WIDTH),
     .CKE_WIDTH      (CKE_WIDTH),
     .CLK_WIDTH      (CLK_WIDTH),
     .COL_WIDTH      (COL_WIDTH),
     .CS_BITS        (CS_BITS),
     .CS_NUM         (CS_NUM),
     .CS_WIDTH       (CS_WIDTH),
     .DM_WIDTH       (DM_WIDTH),
     .DQ_WIDTH       (DQ_WIDTH),
     .DQ_BITS        (DQ_BITS),
     .DQ_PER_DQS     (DQ_PER_DQS),
     .DQS_BITS       (DQS_BITS),
     .DQS_WIDTH      (DQS_WIDTH),
     .ODT_WIDTH      (ODT_WIDTH),
     .ROW_WIDTH      (ROW_WIDTH),
     .ADDITIVE_LAT   (ADDITIVE_LAT),
     .BURST_LEN      (BURST_LEN),
     .BURST_TYPE     (BURST_TYPE),
     .CAS_LAT        (CAS_LAT),
     .ECC_ENABLE     (ECC_ENABLE),
     .MULTI_BANK_EN  (MULTI_BANK_EN),
     .ODT_TYPE       (ODT_TYPE),
     .REDUCE_DRV     (REDUCE_DRV),
     .REG_ENABLE     (REG_ENABLE),
     .TREFI_NS       (TREFI_NS),
     .TRAS           (TRAS),
     .TRCD           (TRCD),
     .TRFC           (TRFC),
     .TRP            (TRP),
     .TRTP           (TRTP),
     .TWR            (TWR),
     .TWTR           (TWTR),
     .CLK_PERIOD     (CLK_PERIOD),
     .DDR2_ENABLE    (1),
     .DQS_GATE_EN    (0),
     .IDEL_HIGH_PERF (IDEL_HIGH_PERF),
     .SIM_ONLY       (SIM_ONLY)
     )
    u_mem_if_top_0
      (
       .clk0              (clk0),
       .clk90             (clk90),
       .rst0              (rst0),
       .rst90             (rst90),
       .app_af_cmd        (app_af_cmd),
       .app_af_addr       (app_af_addr),
       .app_af_wren       (app_af_wren),
       .app_wdf_wren      (app_wdf_wren),
       .app_wdf_data      (app_wdf_data),
       .app_wdf_mask_data (app_wdf_mask_data),
       .app_af_afull      (app_af_afull),
       .app_wdf_afull     (app_wdf_afull),
       .rd_data_valid     (rd_data_valid),
       .rd_data_fifo_out  (rd_data_fifo_out),
       .phy_init_done     (phy_init_done),
       .ddr_ck            (ddr2_ck),
       .ddr_ck_n          (ddr2_ck_n),
       .ddr_addr          (ddr2_a),
       .ddr_ba            (ddr2_ba),
       .ddr_ras_n         (ddr2_ras_n),
       .ddr_cas_n         (ddr2_cas_n),
       .ddr_we_n          (ddr2_we_n),
       .ddr_cs_n          (ddr2_cs_n),
       .ddr_cke           (ddr2_cke),
       .ddr_odt           (ddr2_odt),
       .ddr_dm            (ddr2_dm),
       .ddr_dqs           (ddr2_dqs),
       .ddr_dqs_n         (ddr2_dqs_n),
       .ddr_dq            (ddr2_dq)
       );


endmodule