//*****************************************************************************// Copyright (c) 2006 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, Inc.// All Rights Reserved//*****************************************************************************//   ____  ____//  /   /\/   /// /___/  \  /    Vendor: Xilinx// \   \   \/     Version: $Name: i+IP+125372 $//  \   \         Application: MIG//  /   /         Filename: mem_interface_top_infrastructure.v// /___/   /\     Date Last Modified: $Date: 2008/05/29 13:49:32 $// \   \  /  \    Date Created: Wed Aug 16 2006//  \___\/\___\////Device: Virtex-5//Design Name: DDR2//Purpose://   Clock generation/distribution and reset synchronization//Reference://Revision History: Added support for ML505 which shares a 200 MHz clock//                  between IDELAY_CTRL and the DDR2 controller//*****************************************************************************`timescale 1ns/1psmodule mem_interface_top_infrastructure #  (   parameter CLK_PERIOD    = 5000,   parameter DLL_FREQ_MODE = "HIGH",   parameter RST_ACT_LOW  = 1   )  (   input  sys_clk_p,   input  sys_clk_n,   input  clk200_p,   input  clk200_n,   output clk0,   output clk90,   output clk200,   input  sys_rst_n,   input  idelay_ctrl_rdy,   output rst0,   output rst90,   output rst200   );  // # of clock cycles to delay deassertion of reset. Needs to be a fairly  // high number not so much for metastability protection, but to give time  // for reset (i.e. stable clock cycles) to propagate through all state  // machines and to all control signals (i.e. not all control signals have  // resets, instead they rely on base state logic being reset, and the effect  // of that reset propagating through the logic). Need this because we may not  // be getting stable clock cycles while reset asserted (i.e. since reset  // depends on DCM lock status)  localparam RST_SYNC_NUM = 25;  localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0;    wire                   clk0_bufg;  wire                   clk90_bufg;  wire                   clk200_bufg;  wire                   clk200_ibufg;  wire                   dcm_clk0;  wire                   dcm_clk90;  wire                   dcm_lock;  reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;  reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */;  reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */;  wire                   rst_tmp;`ifdef ML505  wire                   sys_clk_ibufg;`endif  wire                   sys_rst;  assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;  assign clk0    = clk0_bufg;  assign clk90   = clk90_bufg;  assign clk200  = clk200_bufg;    //***************************************************************************  // Differential input clock input buffers  //***************************************************************************`ifdef ML505      IBUFGDS_LVPECL_25 u_ibufg_sys_clk    (     .I  (sys_clk_p),     .IB (sys_clk_n),     .O  (sys_clk_ibufg)     );`endif  IBUFGDS_LVPECL_25 u_ibufg_clk200    (     .I  (clk200_p),     .IB (clk200_n),     .O  (clk200_ibufg)     );  //***************************************************************************  // Global clock generation and distribution  //***************************************************************************  DCM_BASE #    (     .CLKIN_PERIOD          (CLK_PERIOD_NS),     .DLL_FREQUENCY_MODE    (DLL_FREQ_MODE),     .DUTY_CYCLE_CORRECTION ("TRUE"),     .FACTORY_JF            (16'hF0F0)     )    u_dcm_base      (       .CLK0      (dcm_clk0),       .CLK180    (),       .CLK270    (),       .CLK2X     (),       .CLK2X180  (),       .CLK90     (dcm_clk90),       .CLKDV     (),       .CLKFX     (),       .CLKFX180  (),       .LOCKED    (dcm_lock),       .CLKFB     (clk0_bufg),`ifndef ML505       .CLKIN     (clk200_ibufg),`else       .CLKIN     (sys_clk_ibufg),`endif       .RST       (sys_rst)       );/*pll125 pll125(               .CLKIN1_IBUFG(clk200_ibufg),              .RST_IN(sys_rst),               .CLKFBOUT_OUT(),              .CLKOUT2_BUF(),               .CLKOUT0_BUF(dcm_clk0),               .CLKOUT1_BUF(dcm_clk90),               .LOCKED_OUT(dcm_lock));  */                BUFG u_bufg_clk0     (     .O (clk0_bufg),     .I (dcm_clk0)     );    BUFG u_bufg_clk90     (     .O (clk90_bufg),     .I (dcm_clk90)     );  BUFG u_bufg_clk200     (     .O (clk200_bufg),     .I (clk200_ibufg)     );  //***************************************************************************  // Reset synchronization  // NOTES:  //   1. shut down the whole operation if the DCM hasn't yet locked (and by  //      inference, this means that external SYS_RST_IN has been asserted -  //      DCM deasserts DCM_LOCK as soon as SYS_RST_IN asserted)  //   2. In the case of all resets except rst200, also assert reset if the  //      IDELAY master controller is not yet ready  //   3. asynchronously assert reset. This was we can assert reset even if  //      there is no clock (needed for things like 3-stating output buffers).  //      reset deassertion is synchronous.  //***************************************************************************  assign rst_tmp = sys_rst | ~dcm_lock | ~idelay_ctrl_rdy;  // synthesis attribute max_fanout of rst0_sync_r is 10  always @(posedge clk0_bufg or posedge rst_tmp)    if (rst_tmp)      rst0_sync_r <= {RST_SYNC_NUM{1'b1}};    else      // logical left shift by one (pads with 0)      rst0_sync_r <= rst0_sync_r << 1;  // synthesis attribute max_fanout of rst90_sync_r is 10  always @(posedge clk90_bufg or posedge rst_tmp)    if (rst_tmp)      rst90_sync_r <= {RST_SYNC_NUM{1'b1}};    else      rst90_sync_r <= rst90_sync_r << 1;  // make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg   // synthesis attribute max_fanout of rst200_sync_r is 10  always @(posedge clk200_bufg or negedge dcm_lock)    if (!dcm_lock)      rst200_sync_r <= {RST_SYNC_NUM{1'b1}};    else      rst200_sync_r <= rst200_sync_r << 1;  assign rst0   = rst0_sync_r[RST_SYNC_NUM-1];  assign rst90  = rst90_sync_r[RST_SYNC_NUM-1];  assign rst200 = rst200_sync_r[RST_SYNC_NUM-1];endmodule