-- MARCO ANTONIO HIDALGO CUNHA-- EA-277 Introdu玢o a Linguagem VHDL - Professor Roberto D'AMORE -- November 6th of 2007 -- awallon@ita.br  -- EX#9.7.3) Divisor do Tipo com restaura玢o sequencial. library divisor ;use divisor.pkg_divisor.ALL ;-- bit_width was instantiated in the pkg_divisior pack, -- it could be declared as a generic as well.  entity divisor is    Port ( a : in bit_vector ( (bit_width - 1) downto 0) ;           b : in bit_vector ( (bit_width - 2) downto 0) ;           q : out bit_vector( (bit_width - 1) downto 0) ;	       ld : inout bit;	       ck : in bit );end divisor;architecture Behavioral of divisor is-- The following is the signals to be used as local ones.      signal aux_qs : bit_vector( 0 to 10 ) ;   signal qs     : bit_vector( 0 to 4 ) ;	signal ri,ri1 : bit_vector( 0 to 2 ) ;	signal ci1    : bit_vector( 0 to 3 ) ;  		signal ld1, ld2, gp4 : bit ;  	signal notb   : bit_vector ( (bit_width - 2) downto 0);		signal ds     : bit ;		begin -------------------------------------------------------------- XXXXXXXXXXXXXXXXXXXXXXX CONTROL XXXXXXXXXXXXXXXXXXXXXX --------------------------------------------------------------	 --  sub_control : process(q)--  begin--      if q /= "00000" then--          ld <= '0';--          else--          ld <= '1';--       end if;--  end process sub_control;     CTRL : controller PORT MAP ( ck => ck,                             ctrl => ld,                              ld1 => ld1,                              ld2 => ld2 ) ; -------------------------------------------------------------- XXXXXXXXXXXXXXXXXXXX Register n#0 XXXXXXXXXXXXXXXXXXXX --------------------------------------------------------------		 						-- NOTE THAT ALL values(e.g : a, ck) in the entity do not need-- to be instanciated as local signal herein.( architecture )     REG0  : gp_reg PORT MAP ( a => a,                          ck => ck,                         ld1 => ld1,                         gp4 => gp4 ) ;------------------------------------------------------------------ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ----------------------------------------------------------------		 						 notb <= not b ;   GLOBAL : FOR i IN 0 TO 3 GENERATE      first : if ( i = 0 ) GENERATE      BLK0  : x_blk PORT MAP ( bi => notb(0),                               ci => '1',  		  	 	                   ri => gp4,  							         	qi => ds,   				                  ci1 => ci1(i), 							         ri1 => ri1(i) ) ;       					       END GENERATE first ;     	 second : if (i > 0) and ( i < 3) GENERATE 	   BLK_MIDDLE : x_blk PORT MAP ( bi => notb(i),                                    ci => ci1(i-1),  		                              ri => ri(i-1), 			 		                     qi => ds, 				                       ci1 => ci1(i), 				  			              ri1 => ri1(i) ) ;					            	   END GENERATE second ;	   	  thirth : if ( i = 3) GENERATE 	   BLK_END : y_blk PORT MAP ( bi => notb(i),                                 ci => ci1(i-1), 				 		               ri => ri(i-1),								        ci1 => ds ) ; 			   END GENERATE thirth ;	    END GENERATE GLOBAL ;   ------------------------------------------------------------------ XXXXXXXXXXXXXXXXXXXX Register n#1 XXXXXXXXXXXXXXXXXXXX ----------------------------------------------------------------		       	  ri <= ri1 when ck'event and ck = '1' ;		                	------------------------------------------------------------------ XXXXXXXXXXXXXXXXXXXX Register n#2 XXXXXXXXXXXXXXXXXXXX ----------------------------------------------------------------		 						REG2 : process(ck)variable i : natural := 0;begin             if ( ck'event and ck='1' ) then                        if ( i <= 8 ) then            aux_qs(i) <= ds ;           i := i + 1;        end if;                       if ( i = 8 ) then             qs <= aux_qs(2 to 6) ;        end if ;                             end if ;           end process REG2 ;        ---------------------------------------------------------------- XXXXXXXXXXXXXXXXXXXXX Register n#3 XXXXXXXXXXXXXXXXXXXXX ----------------------------------------------------------------				 						 REG3 : exit_reg PORT MAP ( qs => qs,                              q => q,                            ck => ck,                            ld2 => ld2 ) ;   								  							   							   							   								 end Behavioral;