----------------------------------------------------------------------------
----------------------------------------------------------------------------
--  The Free IP Project
--  VHDL Free-RAM Core
--  (c) 1999, The Free IP Project and David Kessner
--
--
--  FREE IP GENERAL PUBLIC LICENSE
--  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
--  1.  You may copy and distribute verbatim copies of this core, as long
--      as this file, and the other associated files, remain intact and
--      unmodified.  Modifications are outlined below.  
--  2.  You may use this core in any way, be it academic, commercial, or
--      military.  Modified or not.  
--  3.  Distribution of this core must be free of charge.  Charging is
--      allowed only for value added services.  Value added services
--      would include copying fees, modifications, customizations, and
--      inclusion in other products.
--  4.  If a modified source code is distributed, the original unmodified
--      source code must also be included (or a link to the Free IP web
--      site).  In the modified source code there must be clear
--      identification of the modified version.
--  5.  Visit the Free IP web site for additional information.
--      http://www.free-ip.com
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


package ram_lib is
  component ram_dp
    generic (addr_bits		:integer;
             data_bits		:integer;
             register_out_flag	:integer := 0;
             block_type		:integer := 0);
    port (reset		:in  std_logic;
          wr_clk	:in  std_logic;
    	  wr_en	    	:in  std_logic;
          wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          wr_data	:in  std_logic_vector(data_bits-1 downto 0);
	  rd_clk	:in  std_logic;
          rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          rd_data	:out std_logic_vector(data_bits-1 downto 0)
         );
  end component;
end ram_lib;


----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram_dp is
    generic (addr_bits	:integer;
             data_bits		:integer;
             register_out_flag	:integer := 0);
    port (reset		:in  std_logic;
          wr_clk	:in  std_logic;
    	  wr_en	        :in  std_logic;
          wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          wr_data	:in  std_logic_vector(data_bits-1 downto 0);
	  rd_clk	:in  std_logic;
          rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          rd_data	:out std_logic_vector(data_bits-1 downto 0)
         );
end ram_dp;


architecture arch_ram_dp of ram_dp is
  COMPONENT lpm_ram_dp
    GENERIC (LPM_WIDTH: POSITIVE;
             LPM_WIDTHAD: POSITIVE;
             LPM_NUMWORDS: NATURAL := 0;
             LPM_TYPE: STRING := "LPM_RAM_DP";
             LPM_INDATA: STRING := "REGISTERED";
             LPM_OUTDATA: STRING := "REGISTERED";
             LPM_RDADDRESS_CONTROL: STRING := "REGISTERED";
             LPM_WRADDRESS_CONTROL: STRING := "REGISTERED";
             LPM_FILE: STRING := "UNUSED";
             LPM_HINT: STRING := "UNUSED"
           );
    PORT (   rdaddress, wraddress: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
             rdclock, wrclock: IN STD_LOGIC := '0';
             rden, rdclken, wrclken: IN STD_LOGIC := '1';
             wren: IN STD_LOGIC; 
             data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
             q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
  END COMPONENT;

  signal always_one :std_logic;  
begin
  always_one <= '1';

  RAM_BUF: if register_out_flag=0 generate
    RAM1:  component lpm_ram_dp 
	  	    generic map
			  (LPM_WIDTH => data_bits, 
			   LPM_WIDTHAD =>  addr_bits, 
			   -- The following line is commented out because
			   -- Quartus doesn't support the exponent operator.
			   -- Fortunately, this line is not needed
			   --LPM_NUMWORDS =>  2**addr_bits, 
			   LPM_TYPE => "LPM_RAM_DP",
			   LPM_INDATA => "REGISTERED", 
			   LPM_OUTDATA => "UNREGISTERED", 
			   LPM_RDADDRESS_CONTROL => "UNREGISTERED", 
			   LPM_WRADDRESS_CONTROL => "REGISTERED", 
			   LPM_FILE => "UNUSED", 
			   LPM_HINT => "UNUSED")
			port map 
			  (rdaddress => rd_addr,
			   wraddress => wr_addr,
			   data => wr_data,
			   wrclock => wr_clk,
	           	   rden => always_one,
			   rdclken => always_one,
			   wrclken => always_one,
        	           wren => wr_en,
                           q => rd_data); 
  end generate RAM_BUF;

  RAM_REG: if register_out_flag/=0 generate
    RAM1:  component lpm_ram_dp 
	  	    generic map
			  (LPM_WIDTH => data_bits, 
			   LPM_WIDTHAD =>  addr_bits,
			   -- The following line is commented out because
			   -- Quartus doesn't support the exponent operator.
			   -- Fortunately, this line is not needed
			   --LPM_NUMWORDS =>  2**addr_bits, 
			   LPM_TYPE => "LPM_RAM_DP",
			   LPM_INDATA => "REGISTERED", 
			   LPM_OUTDATA => "REGISTERED", 
			   LPM_RDADDRESS_CONTROL => "UNREGISTERED", 
			   LPM_WRADDRESS_CONTROL => "REGISTERED", 
			   LPM_FILE => "UNUSED", 
			   LPM_HINT => "UNUSED")
			port map 
			  (rdaddress => rd_addr,
			   wraddress => wr_addr,
			   data => wr_data,
			   rdclock => rd_clk,
			   wrclock => wr_clk,
	           	   rden => always_one,
			   rdclken => always_one,
			   wrclken => always_one,
        	           wren => wr_en,
                           q => rd_data); 
  end generate RAM_REG;

end arch_ram_dp;

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