----------------------------------------------------------------------------
----------------------------------------------------------------------------
--  The Free IP Project
--  VHDL Free-RAM Core
--  (c) 1999, The Free IP Project and David Kessner
--
--
--  FREE IP GENERAL PUBLIC LICENSE
--  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
--  1.  You may copy and distribute verbatim copies of this core, as long
--      as this file, and the other associated files, remain intact and
--      unmodified.  Modifications are outlined below.  
--  2.  You may use this core in any way, be it academic, commercial, or
--      military.  Modified or not.  
--  3.  Distribution of this core must be free of charge.  Charging is
--      allowed only for value added services.  Value added services
--      would include copying fees, modifications, customizations, and
--      inclusion in other products.
--  4.  If a modified source code is distributed, the original unmodified
--      source code must also be included (or a link to the Free IP web
--      site).  In the modified source code there must be clear
--      identification of the modified version.
--  5.  Visit the Free IP web site for additional information.
--      http://www.free-ip.com
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;


entity ram_test is
  port   (reset		:in  std_logic;
          clk		:in  std_logic;
          addr_out	:out std_logic_vector (12 downto 0);
          din_out	:out std_logic_vector (7 downto 0);
          dout_out	:out std_logic_vector (7 downto 0);
          rand_out	:out std_logic_vector (7 downto 0);
          we_out	:out std_logic;
          failure_out	:out std_logic);
end ram_test;


architecture arch_ram_test of ram_test is
  type STATES is (WRITE, READ);
  signal state		:states;
  signal state_reg	:states;

  signal addr		:std_logic_vector (addr_out'range);
  signal din		:std_logic_vector (din_out'range);

  signal dout		:std_logic_vector (din'range);
  signal write_enable	:std_logic;

  signal mask		:std_logic_vector (31 downto 0);
  signal rand1		:std_logic_vector (mask'range);
  signal rand2		:std_logic_vector (mask'range);
  signal rand2_reg 	:std_logic_vector (mask'range);

  signal addr_top	:std_logic;
  signal addr_max	:std_logic_vector (addr'range);
  
  signal failure 	:std_logic;

begin
  addr_out <= addr;
  din_out <= din;
  dout_out <= dout;
  rand_out <= rand2_reg(rand_out'range);
  we_out <= write_enable;

  mask <= "10100011000000000000000000000000";  -- 0xA3000000



  -- The address counter
  process (reset, clk)
  begin
    if reset='1' then
      addr <= (others=>'0');
    elsif clk'event and clk='1' then
      addr <= addr + 1;
    end if;
  end process;


  -- The addr_top signal
  addr_max <= (others=>'1');
  addr_top <= '1' when addr=addr_max else '0';
  

  -- The state machine
  process (reset, clk)
  begin
    if reset='1' then
      state <= WRITE;
    elsif clk'event and clk='1' then
      case state is
        when WRITE =>
            if addr_top='1' then
              state <= READ;
            end if;
            
        when READ =>
            if addr_top='1' then
              state <= WRITE;
            end if;
            
        when others =>
            state <= WRITE;
      end case;
    end if;
  end process;

  -- Generate a delayed version of state
  process (reset, clk)
  begin
    if reset='1' then
      state_reg <= WRITE;
    elsif clk'event and clk='1' then
      state_reg <= state;
    end if;
  end process;


  -- The write data generator
  process (reset, clk)
  begin
    if reset='1' then
      rand1 <= (others => '1');
    elsif clk'event and clk='1' then
      if state=WRITE then
        if rand1(0)='1' then
          rand1 <= ("0" & rand1(rand1'high downto 1)) xor mask;
        else
          rand1 <= ("0" & rand1(rand1'high downto 1));
        end if;
      end if;
    end if;
  end process;

  din <= rand1(din'range);
  

  -- The READ data generator
  process (reset, clk)
  begin
    if reset='1' then
      rand2 <= (others => '1');
      rand2_reg <= (others => '1');
    elsif clk'event and clk='1' then
      rand2_reg <= rand2;
      
      if state=READ then
        if rand2(0)='1' then
          rand2 <= ("0" & rand2(rand2'high downto 1)) xor mask;
        else
          rand2 <= ("0" & rand2(rand2'high downto 1));
        end if;
      end if;
    end if;
  end process;


  -- Write Enable
  process (reset, clk)
  begin
    if reset='1' then
      write_enable <= '1';
    elsif clk'event and clk='1' then
      if addr_top='1' then
        if state=READ then
          write_enable <= '1';
        else
          write_enable <= '0';
        end if;
      elsif state=WRITE then
        write_enable <= '1';
      else
        write_enable <= '0';
      end if;
    end if;
  end process;


  -- The RAM under test
  U1: ram_dp
  	generic map (addr_bits => addr'high+1,
  	             data_bits => din'high+1,
  	             register_out_flag => 1,
  	             block_type => 0)
  	port map (reset, clk, write_enable, addr, din, clk, addr, dout);

  -- Generate the failure signal
  process (reset, clk)
  begin
    if reset='1' then
      failure <= '0';
    elsif clk'event and clk='1' then
      if failure='0' then
        if state_reg=READ then
          if dout/=rand2_reg(dout'range) then
            failure <= '1';
          end if;
        end if;
      end if;
    end if;
  end process;


  failure_out <= failure;
  
end arch_ram_test;