?? obuftds_fdp_lvpecl.edf
字號:
(edif Xilinx_edif (edifVersion 2 0 0) (edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written (timeStamp 2000 2 23 16 46 0)
(program "Xilinx" (Version "2.23.2000"))
(dataOrigin "Xilinx") (author "XAPP133")
)
)
(external (rename xfpga_virtexe_7 "xfpga_virtexe-7") (edifLevel 0)
(technology (numberDefinition))
(cell INV (cellType GENERIC)
(view Netlist_representation (viewType NETLIST)
(interface (port O (direction OUTPUT)) (port I (direction INPUT)))
)
)
(cell FDP (cellType GENERIC)
(view Netlist_representation (viewType NETLIST)
(interface (port Q (direction OUTPUT)) (port D (direction INPUT))
(port C (direction INPUT)) (port PRE (direction INPUT))
)
)
)
(cell FDC (cellType GENERIC)
(view Netlist_representation (viewType NETLIST)
(interface (port Q (direction OUTPUT)) (port D (direction INPUT))
(port C (direction INPUT)) (port CLR (direction INPUT))
)
)
)
(cell OBUFT_LVPECL (cellType GENERIC)
(view Netlist_representation (viewType NETLIST)
(interface (port O (direction OUTPUT)) (port I (direction INPUT))
(port T (direction INPUT))
)
)
)
)
(library DESIGNS (edifLevel 0) (technology (numberDefinition))
(cell OBUFTDS_FDP_LVPECL (cellType GENERIC)
(view Netlist_representation (viewType NETLIST)
(interface (port D (direction INPUT)) (port T (direction INPUT))
(port C (direction INPUT)) (port PRE (direction INPUT))
(port O (direction OUTPUT)) (port OB (direction OUTPUT))
)
(contents
(instance inv_n
(viewRef Netlist_representation
(cellRef INV (libraryRef xfpga_virtexe_7))
)
)
(instance off_p
(viewRef Netlist_representation
(cellRef FDP (libraryRef xfpga_virtexe_7))
)
(property IOB (string "true"))
)
(instance tri_n
(viewRef Netlist_representation
(cellRef FDP (libraryRef xfpga_virtexe_7))
)
(property IOB (string "true"))
)
(instance tri_p
(viewRef Netlist_representation
(cellRef FDP (libraryRef xfpga_virtexe_7))
)
(property IOB (string "true"))
)
(instance off_n
(viewRef Netlist_representation
(cellRef FDC (libraryRef xfpga_virtexe_7))
)
(property IOB (string "true"))
)
(instance pad_p
(viewRef Netlist_representation
(cellRef OBUFT_LVPECL (libraryRef xfpga_virtexe_7))
)
)
(instance pad_n
(viewRef Netlist_representation
(cellRef OBUFT_LVPECL (libraryRef xfpga_virtexe_7))
)
)
(net D
(joined (portRef D) (portRef I (instanceRef inv_n))
(portRef D (instanceRef off_p))
)
)
(net T
(joined (portRef T) (portRef D (instanceRef tri_p))
(portRef D (instanceRef tri_n))
)
)
(net C
(joined (portRef C) (portRef C (instanceRef off_p))
(portRef C (instanceRef off_n)) (portRef C (instanceRef tri_p))
(portRef C (instanceRef tri_n))
)
)
(net q_n
(joined (portRef Q (instanceRef off_n)) (portRef I (instanceRef pad_n)))
)
(net t_p
(joined (portRef Q (instanceRef tri_p)) (portRef T (instanceRef pad_p)))
)
(net PRE
(joined (portRef PRE) (portRef PRE (instanceRef off_p))
(portRef CLR (instanceRef off_n)) (portRef PRE (instanceRef tri_p))
(portRef PRE (instanceRef tri_n))
)
)
(net q_p
(joined (portRef Q (instanceRef off_p)) (portRef I (instanceRef pad_p)))
)
(net O (joined (portRef O) (portRef O (instanceRef pad_p))))
(net OB (joined (portRef OB) (portRef O (instanceRef pad_n))))
(net t_n
(joined (portRef Q (instanceRef tri_n)) (portRef T (instanceRef pad_n)))
)
(net D_n
(joined (portRef O (instanceRef inv_n)) (portRef D (instanceRef off_n)))
)
)
)
)
)
(design Xilinx_edif (cellRef OBUFTDS_FDP_LVPECL (libraryRef DESIGNS)))
)
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -