(edif Xilinx_edif (edifVersion 2 0 0) (edifLevel 0)
 (keywordMap (keywordLevel 0))
 (status
  (written (timeStamp 2000 2 23 16 35 9)
   (program "Xilinx" (Version "2.23.2000"))
   (dataOrigin "Xilinx") (author "XAPP133")
  )
 )
 (external (rename xfpga_virtexe_7 "xfpga_virtexe-7") (edifLevel 0)
  (technology (numberDefinition))
  (cell FDSE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port C (direction INPUT)) (port S (direction INPUT))
     (port CE (direction INPUT))
    )
   )
  )
  (cell IBUF_LVDS (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))
   )
  )
 )
 (library DESIGNS (edifLevel 0) (technology (numberDefinition))
  (cell IBUFDS_FDSE_LVDS (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port I (direction INPUT)) (port IB (direction INPUT))
     (port CE (direction INPUT)) (port C (direction INPUT))
     (port S (direction INPUT)) (port Q (direction OUTPUT))
    )
    (contents
     (instance iff_p
      (viewRef Netlist_representation
       (cellRef FDSE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance pad_p
      (viewRef Netlist_representation
       (cellRef IBUF_LVDS (libraryRef xfpga_virtexe_7))
      )
     )
     (instance pad_n
      (viewRef Netlist_representation
       (cellRef IBUF_LVDS (libraryRef xfpga_virtexe_7))
      )
     )
     (net I (joined (portRef I) (portRef I (instanceRef pad_p))))
     (net IB (joined (portRef IB) (portRef I (instanceRef pad_n))))
     (net CE (joined (portRef CE) (portRef CE (instanceRef iff_p))))
     (net C (joined (portRef C) (portRef C (instanceRef iff_p))))
     (net S (joined (portRef S) (portRef S (instanceRef iff_p))))
     (net Q (joined (portRef Q) (portRef Q (instanceRef iff_p))))
     (net I_w
      (joined (portRef D (instanceRef iff_p)) (portRef O (instanceRef pad_p)))
     )
    )
   )
  )
 )
 (design Xilinx_edif (cellRef IBUFDS_FDSE_LVDS (libraryRef DESIGNS)))
)