(edif Xilinx_edif (edifVersion 2 0 0) (edifLevel 0)
 (keywordMap (keywordLevel 0))
 (status
  (written (timeStamp 2000 2 23 16 45 58)
   (program "Xilinx" (Version "2.23.2000"))
   (dataOrigin "Xilinx") (author "XAPP133")
  )
 )
 (external (rename xfpga_virtexe_7 "xfpga_virtexe-7") (edifLevel 0)
  (technology (numberDefinition))
  (cell INV (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))
   )
  )
  (cell FDCE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port C (direction INPUT)) (port CLR (direction INPUT))
     (port CE (direction INPUT))
    )
   )
  )
  (cell OBUF_LVPECL (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))
   )
  )
  (cell FDPE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port C (direction INPUT)) (port PRE (direction INPUT))
     (port CE (direction INPUT))
    )
   )
  )
 )
 (library DESIGNS (edifLevel 0) (technology (numberDefinition))
  (cell OBUFDS_FDPE_LVPECL (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port D (direction INPUT)) (port CE (direction INPUT))
     (port C (direction INPUT)) (port PRE (direction INPUT))
     (port O (direction OUTPUT)) (port OB (direction OUTPUT))
    )
    (contents
     (instance inv_n
      (viewRef Netlist_representation
       (cellRef INV (libraryRef xfpga_virtexe_7))
      )
     )
     (instance off_p
      (viewRef Netlist_representation
       (cellRef FDPE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance off_n
      (viewRef Netlist_representation
       (cellRef FDCE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance pad_p
      (viewRef Netlist_representation
       (cellRef OBUF_LVPECL (libraryRef xfpga_virtexe_7))
      )
     )
     (instance pad_n
      (viewRef Netlist_representation
       (cellRef OBUF_LVPECL (libraryRef xfpga_virtexe_7))
      )
     )
     (net D
      (joined (portRef D) (portRef I (instanceRef inv_n))
       (portRef D (instanceRef off_p))
      )
     )
     (net CE
      (joined (portRef CE) (portRef CE (instanceRef off_p))
       (portRef CE (instanceRef off_n))
      )
     )
     (net C
      (joined (portRef C) (portRef C (instanceRef off_p))
       (portRef C (instanceRef off_n))
      )
     )
     (net q_n
      (joined (portRef Q (instanceRef off_n)) (portRef I (instanceRef pad_n)))
     )
     (net PRE
      (joined (portRef PRE) (portRef PRE (instanceRef off_p))
       (portRef CLR (instanceRef off_n))
      )
     )
     (net q_p
      (joined (portRef Q (instanceRef off_p)) (portRef I (instanceRef pad_p)))
     )
     (net O (joined (portRef O) (portRef O (instanceRef pad_p))))
     (net OB (joined (portRef OB) (portRef O (instanceRef pad_n))))
     (net D_n
      (joined (portRef O (instanceRef inv_n)) (portRef D (instanceRef off_n)))
     )
    )
   )
  )
 )
 (design Xilinx_edif (cellRef OBUFDS_FDPE_LVPECL (libraryRef DESIGNS)))
)