(edif Xilinx_edif (edifVersion 2 0 0) (edifLevel 0)
 (keywordMap (keywordLevel 0))
 (status
  (written (timeStamp 2000 2 23 16 46 3)
   (program "Xilinx" (Version "2.23.2000"))
   (dataOrigin "Xilinx") (author "XAPP133")
  )
 )
 (external (rename xfpga_virtexe_7 "xfpga_virtexe-7") (edifLevel 0)
  (technology (numberDefinition))
  (cell FDPE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port C (direction INPUT)) (port PRE (direction INPUT))
     (port CE (direction INPUT))
    )
   )
  )
  (cell INV (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))
   )
  )
  (cell FDCE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port C (direction INPUT)) (port CLR (direction INPUT))
     (port CE (direction INPUT))
    )
   )
  )
  (cell FDE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port C (direction INPUT)) (port CE (direction INPUT))
    )
   )
  )
  (cell IOBUF_LVPECL (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port O (direction OUTPUT)) (port IO (direction INOUT))
     (port I (direction INPUT)) (port T (direction INPUT))
    )
   )
  )
 )
 (library DESIGNS (edifLevel 0) (technology (numberDefinition))
  (cell GND (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port G (direction OUTPUT)))
   )
  )
  (cell IOBUFDS_FDE_LVPECL (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port D (direction INPUT)) (port T (direction INPUT))
     (port CE (direction INPUT)) (port C (direction INPUT))
     (port Q (direction OUTPUT)) (port IO (direction INOUT))
     (port IOB (direction INOUT))
    )
    (contents (instance Logic0 (viewRef Netlist_representation (cellRef GND)))
     (instance tri_n
      (viewRef Netlist_representation
       (cellRef FDPE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance inv_n
      (viewRef Netlist_representation
       (cellRef INV (libraryRef xfpga_virtexe_7))
      )
     )
     (instance off_p
      (viewRef Netlist_representation
       (cellRef FDCE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance off_n
      (viewRef Netlist_representation
       (cellRef FDPE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance iff_p
      (viewRef Netlist_representation
       (cellRef FDE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance pad_p
      (viewRef Netlist_representation
       (cellRef IOBUF_LVPECL (libraryRef xfpga_virtexe_7))
      )
     )
     (instance tri_p
      (viewRef Netlist_representation
       (cellRef FDPE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance pad_n
      (viewRef Netlist_representation
       (cellRef IOBUF_LVPECL (libraryRef xfpga_virtexe_7))
      )
     )
     (net CLR
      (joined (portRef CLR (instanceRef off_p))
       (portRef PRE (instanceRef off_n)) (portRef PRE (instanceRef tri_p))
       (portRef PRE (instanceRef tri_n)) (portRef G (instanceRef Logic0))
      )
     )
     (net D
      (joined (portRef D) (portRef I (instanceRef inv_n))
       (portRef D (instanceRef off_p))
      )
     )
     (net IO (joined (portRef IO) (portRef IO (instanceRef pad_p))))
     (net t_p
      (joined (portRef Q (instanceRef tri_p)) (portRef T (instanceRef pad_p)))
     )
     (net q_n
      (joined (portRef Q (instanceRef off_n)) (portRef I (instanceRef pad_n)))
     )
     (net T
      (joined (portRef T) (portRef D (instanceRef tri_p))
       (portRef D (instanceRef tri_n))
      )
     )
     (net C
      (joined (portRef C) (portRef C (instanceRef off_p))
       (portRef C (instanceRef off_n)) (portRef C (instanceRef tri_p))
       (portRef C (instanceRef tri_n)) (portRef C (instanceRef iff_p))
      )
     )
     (net CE
      (joined (portRef CE) (portRef CE (instanceRef off_p))
       (portRef CE (instanceRef off_n)) (portRef CE (instanceRef tri_p))
       (portRef CE (instanceRef tri_n)) (portRef CE (instanceRef iff_p))
      )
     )
     (net q_p
      (joined (portRef Q (instanceRef off_p)) (portRef I (instanceRef pad_p)))
     )
     (net Q (joined (portRef Q) (portRef Q (instanceRef iff_p))))
     (net t_n
      (joined (portRef Q (instanceRef tri_n)) (portRef T (instanceRef pad_n)))
     )
     (net D_n
      (joined (portRef O (instanceRef inv_n)) (portRef D (instanceRef off_n)))
     )
     (net i_p
      (joined (portRef D (instanceRef iff_p)) (portRef O (instanceRef pad_p)))
     )
     (net IOB (joined (portRef IOB) (portRef IO (instanceRef pad_n))))
    )
   )
  )
 )
 (design Xilinx_edif (cellRef IOBUFDS_FDE_LVPECL (libraryRef DESIGNS)))
)