library verilog;use verilog.vl_types.all;entity traffic_sm is    generic(        idle            : integer := 1;        y1_r1_s1        : integer := 2;        g1_r2_s2        : integer := 4;        y1_r2_s3        : integer := 8;        r1_y2_s4        : integer := 16;        r1_g2_s5        : integer := 32;        r1_y2_s6        : integer := 64;        red             : integer := 1;        yellow          : integer := 2;        green           : integer := 4    );    port(        clk             : in     vl_logic;        rst_n           : in     vl_logic;        enable          : in     vl_logic;        counter_24      : in     vl_logic_vector(4 downto 0);        enable_sig      : out    vl_logic;        road1_out       : out    vl_logic_vector(2 downto 0);        road2_out       : out    vl_logic_vector(2 downto 0)    );end traffic_sm;