library verilog;use verilog.vl_types.all;entity traffic_controller is    port(        clk             : in     vl_logic;        rst_n           : in     vl_logic;        enable          : in     vl_logic;        road1_out       : out    vl_logic_vector(2 downto 0);        road2_out       : out    vl_logic_vector(2 downto 0)    );end traffic_controller;