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-- Company: 
-- Engineer:
--
-- Create Date:   01:32:58 01/20/2006
-- Design Name:   vga
-- Module Name:   test.vhd
-- Project Name:  vga
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: vga
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT vga
	PORT(
		reset : IN std_logic;
		clk_f : IN std_logic;    
		hsync : INOUT std_logic;
		vsync : INOUT std_logic;      
		rgb : OUT std_logic_vector(2 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset :  std_logic := '0';
	SIGNAL clk_f :  std_logic := '0';

	--BiDirs
	SIGNAL hsync :  std_logic;
	SIGNAL vsync :  std_logic;

	--Outputs
	SIGNAL rgb :  std_logic_vector(2 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: vga PORT MAP(
		reset => reset,
		clk_f => clk_f,
		hsync => hsync,
		vsync => vsync,
		rgb => rgb
	);

tb : PROCESS
   BEGIN
		reset  <= transport '0';
		WAIT FOR 20 ns;
		reset  <= transport '1';
		WAIT FOR 40 ns;
		wait;
   END PROCESS;
	
	PROCESS		begin			clk_f <= '1'; wait for 20 ns;			clk_f <= '0'; wait for 20 ns;	END PROCESS;

END;