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-- Company: 
-- Engineer:
--
-- Create Date:   00:44:54 01/19/2006
-- Design Name:   lcdgraph
-- Module Name:   test.vhd
-- Project Name:  08_LCD_graph
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: lcdgraph
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT lcdgraph
	PORT(
		clk : IN std_logic;          
		E_LCD : OUT std_logic;
		DI_LCD : OUT std_logic;
		CS1_LCD : OUT std_logic;
		CS2_LCD : OUT std_logic;
		RST_LCD : OUT std_logic;
		D_LCD : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';

	--Outputs
	SIGNAL E_LCD :  std_logic;
	SIGNAL DI_LCD :  std_logic;
	SIGNAL CS1_LCD :  std_logic;
	SIGNAL CS2_LCD :  std_logic;
	SIGNAL RST_LCD :  std_logic;
	SIGNAL D_LCD :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: lcdgraph PORT MAP(
		clk => clk,
		E_LCD => E_LCD,
		DI_LCD => DI_LCD,
		CS1_LCD => CS1_LCD,
		CS2_LCD => CS2_LCD,
		RST_LCD => RST_LCD,
		D_LCD => D_LCD
	);

		tb : PROCESS
	   BEGIN			clk<= '1'; wait for 10 ns;			clk<= '0'; wait for 10 ns;	END PROCESS; 

END;